JPS6218052Y2 - - Google Patents

Info

Publication number
JPS6218052Y2
JPS6218052Y2 JP19458782U JP19458782U JPS6218052Y2 JP S6218052 Y2 JPS6218052 Y2 JP S6218052Y2 JP 19458782 U JP19458782 U JP 19458782U JP 19458782 U JP19458782 U JP 19458782U JP S6218052 Y2 JPS6218052 Y2 JP S6218052Y2
Authority
JP
Japan
Prior art keywords
resin
sealed
chip
lead
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19458782U
Other languages
English (en)
Japanese (ja)
Other versions
JPS5998650U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1982194587U priority Critical patent/JPS5998650U/ja
Publication of JPS5998650U publication Critical patent/JPS5998650U/ja
Application granted granted Critical
Publication of JPS6218052Y2 publication Critical patent/JPS6218052Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1982194587U 1982-12-22 1982-12-22 樹脂封止型モジユ−ル Granted JPS5998650U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982194587U JPS5998650U (ja) 1982-12-22 1982-12-22 樹脂封止型モジユ−ル

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982194587U JPS5998650U (ja) 1982-12-22 1982-12-22 樹脂封止型モジユ−ル

Publications (2)

Publication Number Publication Date
JPS5998650U JPS5998650U (ja) 1984-07-04
JPS6218052Y2 true JPS6218052Y2 (enFirst) 1987-05-09

Family

ID=30418200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982194587U Granted JPS5998650U (ja) 1982-12-22 1982-12-22 樹脂封止型モジユ−ル

Country Status (1)

Country Link
JP (1) JPS5998650U (enFirst)

Also Published As

Publication number Publication date
JPS5998650U (ja) 1984-07-04

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