JPS62177946A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62177946A
JPS62177946A JP61019411A JP1941186A JPS62177946A JP S62177946 A JPS62177946 A JP S62177946A JP 61019411 A JP61019411 A JP 61019411A JP 1941186 A JP1941186 A JP 1941186A JP S62177946 A JPS62177946 A JP S62177946A
Authority
JP
Japan
Prior art keywords
metal
layer
metal layer
aluminum
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61019411A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Hirano
平野 芳行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61019411A priority Critical patent/JPS62177946A/en
Publication of JPS62177946A publication Critical patent/JPS62177946A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To perform the etching of a metal layer except a pad electrode only by one step by forming a metal layer under a metal bump in a self-aligning manner by an electrolessly plating method. CONSTITUTION:An aluminum pad electrode 3 and an insulating film 4 are formed on an insulating film 2 on a semiconductor substrate 1, and the film on the electrode 3 is removed. The entire surface is coated with a metal layer 5 of Cr or the like, and an aluminum layer 6 is formed on the layer 5. A photosensitive resin film 7 remains on a region to be formed with a metal bump, and the aluminum layer except this region is oxidized to alter it to an aluminum oxide film 8. The film 7 and the film 6 under the film 7 are removed, and a metal layer 9 of Cu or the like is formed by an electrolessly plating method on the layer 5. Then, with the layer 9 as a plating electrode a metal bump 10 is formed of Au, Cu or the like. Thereafter, with the bump 10 as a mask the layer 8 and the layer 5 are removed by etching. Then, after the bump is formed, the etching of the metal layer is performed only by one step to prevent the pad electrode from being damaged due to the etching.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に金属バンプ
を有する半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having metal bumps.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置の製造方法において、例えは
ギヤングボンディングに用いる金属バンプは1通常第2
図(al〜(dlに示すような製造工程で作られている
。すなわち、半導体基板21上に形成されたシリコン酸
化膜等の第1の絶縁膜22にパッド電極形成用のアルミ
ニウム膜をたとえば、 1,0.[1程度の厚さで被着
せしめ、パウド電極部分23を残し信金除去する。しか
る後、化学気相成長(CVD)法で形成した酸化シリコ
ン膜等の第2の絶縁膜24によシ全面を被覆し、アルミ
ニウムのパッド電極23の上に′電極数9出し用開孔2
5全形成する(第2図(a))。
Conventionally, in the manufacturing method of this type of semiconductor device, for example, the metal bumps used for gigantic bonding are
It is manufactured by the manufacturing process shown in Figures (al to (dl). That is, an aluminum film for forming a pad electrode is coated on a first insulating film 22 such as a silicon oxide film formed on a semiconductor substrate 21, for example. The metal is deposited to a thickness of about 1,0.1, and the metal is removed leaving the powder electrode portion 23. After that, a second insulating film 24 such as a silicon oxide film formed by chemical vapor deposition (CVD) is deposited. The entire surface is covered, and holes 2 for producing 9 electrodes are formed on the aluminum pad electrodes 23.
5. Completely form (Fig. 2(a)).

次いで%複数の金属層26.27’にスパッタ法等によ
り全面に順次積層形成する。この金属層の楊成としてば
Cr−Cu、N 1−Cu、Cr−Cu−Au などの
複数層が用いられる。この金属層のスパッタリングは真
空中において連続的に行なうのが望ましく、またスパッ
タα11にはアルミ膜表面の自然酸化アルミニウム膜を
除去する前処理を行なう方がよい(第2図(b))。
Next, a plurality of metal layers 26 and 27' are sequentially laminated over the entire surface by sputtering or the like. As the material of this metal layer, multiple layers such as Cr-Cu, N1-Cu, Cr-Cu-Au, etc. are used. It is desirable to sputter this metal layer continuously in a vacuum, and it is better to perform a pretreatment for sputtering α11 to remove the natural aluminum oxide film on the surface of the aluminum film (FIG. 2(b)).

更に、前記金属層26.27上にメッキマスク用の感光
性樹脂膜28を全面に被着し、アルミパッド電極上の一
部に金属バンプ形成部の開孔29紮形成する。次に、1
j1」記金属膜26.27金−力の共通電極としてAu
又はCu、手出等を電着せしめ、金属パン130を形成
する。この金属バンプ30は通常10〜20μmの厚さ
に形成する(第1図(C))。その後、感光性樹脂膜2
8及び金属膜26゜27の不要部分全エツチング除去す
ると、最終的な金属バンプ構造が得られる(第1図(d
))。
Further, a photosensitive resin film 28 for use as a plating mask is applied over the entire surface of the metal layer 26, 27, and an opening 29 for a metal bump forming portion is formed in a portion on the aluminum pad electrode. Next, 1
j1'' metal film 26.27 Au as common electrode of gold force
Alternatively, the metal pan 130 is formed by electro-depositing Cu, copper, etc. This metal bump 30 is usually formed to have a thickness of 10 to 20 μm (FIG. 1(C)). After that, the photosensitive resin film 2
8 and the metal film 26 and 27, the final metal bump structure is obtained (see Fig. 1(d)).
)).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置の製造方法は、金属バンプを
形成後yc複数層の金属(1m26,277f:エツチ
ング除去する必要があp、このエウチング叡として1例
えはCrであればフェリシアン化カリウムとカセイソー
ダの混合液、Cuであれは強酸を用いる必要がち)エヅ
チング沿のしみ込みによシバ・ソド電惨等のPJT要部
分の金属がエツチング除去されるなどの問題がある。更
に、金属バンプにCu 下の複数層の金属層にもCu’
(z用いる構造であれは金属バンプ自身もエツチング除
去されるため金h5.バンプの厚さのばらつきも大きく
なるなどの欠点があった。本発明は上記の従来技術の欠
点を改善するために従来技術で金しバンプ下の金JF 
1mか二層であるためエツチングに難点があったものを
無電解メッキ法を利用することにより、金属層のエラチ
ンブラー)曽のみとした製造方法を捉供することを目的
とする。
In the conventional semiconductor device manufacturing method described above, after forming metal bumps, it is necessary to remove multiple layers of metal (1m26, 277f) by etching.For example, in the case of Cr, potassium ferricyanide and caustic soda are If the mixed solution is Cu, it is necessary to use a strong acid) There are problems such as the metal in the important parts of the PJT such as Shiba and Sodo Densai being etched away due to seepage along the etching. Furthermore, Cu is present on the metal bumps and Cu' is also present on the multiple metal layers below.
(In the structure using Z, the metal bumps themselves are also etched away, so there are drawbacks such as large variations in the thickness of the gold h5. Making money with technology and making money under the bump JF
The purpose of the present invention is to provide a manufacturing method that only requires an elastomeric layer of the metal layer, by using an electroless plating method, since etching was difficult due to the thickness of 1 m or 2 layers.

〔問題点全解決するための手段〕[Means to solve all problems]

本発明の半導体装置の製造方法は、半導体基体の一工面
に形成された第1の絶縁膜上に所定形状の金属層全形成
する工程と、前記金属電極に接して全面VC,第2の絶
縁膜を形成し、その所定領域に前記金属電極上面に通ず
る開孔音形成する工程と、前記開孔ゲふくむ前記第2の
絶縁膜上に、第1の金属層とアルミニウム層を順次積層
形成する工程と、前記アルミニウム層のうち、前記金属
電極上の所足幀域以外を陽極酢化法葡用いて、全て酸化
アルミニウム層に変える工程と、前記所定頭載のアルミ
ニウム層會蝕刻除去し、前記第1の金属層全露出せしめ
る工程と、露出した前記第1の金属層上に無電解メッキ
法により第2の金属層全形成する工程と、前記第2の金
属層全メ・ンキ電極として電解メッキ法により前記第2
の金属層に接して第3の金属層層形成する工程と、前記
第3の金属層全マスクとして、前記酸化アルミニウム層
及び第1の金属層全蝕刻除去する工程を含むことを特徴
とする。
The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a metal layer in a predetermined shape entirely on a first insulating film formed on one surface of a semiconductor substrate; forming a film and forming a hole in a predetermined region thereof leading to the upper surface of the metal electrode; and sequentially laminating a first metal layer and an aluminum layer on the second insulating film including the hole. a step of converting all of the aluminum layer other than the area on the metal electrode into an aluminum oxide layer using an anodic acetate method; removing the predetermined aluminum layer by etching; a step of fully exposing a first metal layer; a step of fully forming a second metal layer on the exposed first metal layer by electroless plating; and a step of fully forming a second metal layer on the exposed first metal layer; Said second layer by plating method.
The method is characterized by comprising the steps of: forming a third metal layer in contact with the metal layer; and removing the aluminum oxide layer and the first metal layer by etching, using the entire third metal layer as a mask.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図[a+〜げ)は本発明の一実施例の工程順縦断面
図である。
FIG. 1 [a+ to ge] is a vertical cross-sectional view of an embodiment of the present invention in the order of steps.

半導体基板lの一主面に熱酸化法等によシ絶縁膜2?形
成し、この上に半導体素子間を接続するアルミ配線(図
示せず)及びアルミバヅド電極3を形成する。更にアル
ミ配線及びアルミパッド電極上に保@膜として、CVD
法により絶縁膜4を形成する。そして、アルミパッド電
極3上の絶縁4の一部にホトエツチング法により外部へ
のとシ出し電極用の開孔を形成する(第1図(a))。
An insulating film 2 is formed on one main surface of the semiconductor substrate l by thermal oxidation or the like. Aluminum interconnects (not shown) and aluminum bud electrodes 3 are formed thereon to connect the semiconductor elements. Furthermore, CVD is applied as a protective film on aluminum wiring and aluminum pad electrodes.
An insulating film 4 is formed by a method. Then, an opening for an external electrode is formed in a part of the insulation 4 on the aluminum pad electrode 3 by photoetching (FIG. 1(a)).

次に、スパッタ法などにより、金属層5.たとえばCr
またはTiミラ面に′4M、看する。この金属層5は、
金かバンプの接着層として金属バンプ下に残るものであ
る。
Next, a metal layer 5. is formed by sputtering or the like. For example, Cr
Or look at '4M on the Ti mirror surface. This metal layer 5 is
The gold remains under the metal bump as an adhesive layer for the bump.

その厚さとしては10007V〜5000A  のもの
が用いられる。絖いて、スパッタ法等ゲ用いてアルミニ
ウム層6を例えば5000Aの厚さで形成し、アルミニ
ウム層6上の金属バンプ形成手足領域に選択的に感光性
樹脂膜7全残す(第1図(b))。
The thickness used is 10007V to 5000A. Then, an aluminum layer 6 is formed to a thickness of, for example, 5000 Å using a sputtering method or the like, and the entire photosensitive resin film 7 is selectively left on the metal bump formation limb regions on the aluminum layer 6 (FIG. 1(b)). ).

次に金属バンプ形成予定領域以外のアルミニウム層は陽
極酸化法により酸化アルミニウム膜8に変える。ここで
陽極酸化法とは電解液中でこのアルミニウム全陽極とし
て電圧全印加し、電流を流すことで、アルミニラムラ酸
化アルミニウムに変える方法である。七の後、感光性樹
脂膜7を除去する(第1図(C))。
Next, the aluminum layer other than the area where metal bumps are to be formed is changed into an aluminum oxide film 8 by anodizing. Here, the anodization method is a method in which aluminum is converted into aluminum laminate aluminum oxide by applying a full voltage to the aluminum as an anode in an electrolytic solution and passing a current. After step 7, the photosensitive resin film 7 is removed (FIG. 1(C)).

次に、アルミニウム膜6と酸化アルミニウム膜8との選
択性エツチングが可能で、かつ、下地の金属膜5を除去
しないようなエツチング液、たとえばリン酸を用いて、
アルミニウムをエツチング除去する。しかる後、アルミ
ニウム膜を除去した金鳥膜5の表面上に無電解メッキ法
により第2の金属層9%例えばCuまたはAuを0.5
〜1.0μm程度の厚さに形成する。例えば、下地の金
属層が’I’i、C,のように電解メッキ法ではつきに
くいものでも前処理と無電解メッキ法の組合せによシ金
属膜が成長する条件がある。そして、その後第2の金属
層9をメッキ電極として電解メッキ法によりA11また
はCu1半田の厚さ10〜20μmの金属パンツ會形成
する(第1図(e))。最後に、金属バング10をマス
クとして、酸化アルミニウム層8と、金属層5をそれぞ
れのエツチング液によシ除去する。本発明は、無電解メ
ッキ法を用いて金属バング下に酸化アルミニウム層に対
して自己整合的に1つの金属層全形成している。そのた
め、金属バンプをマスクとした強酸又は強塩基にょるバ
るので、従来問題となっていたエツチング液のしみ込み
によって、配線アルミニウム等がエツチングされてしま
うという問題は非常に少くなる。また、酸化アルミニウ
ム層に対して自己整合的に形成される金属層の材料とし
て、金属バンプと同一のものを用いてもこの金属層を工
ヶチング除去する必要はないので金属バンプがエツチン
グ除去される恐れはなくなる。
Next, using an etching solution such as phosphoric acid that is capable of selectively etching the aluminum film 6 and the aluminum oxide film 8 and does not remove the underlying metal film 5,
Etch away the aluminum. Thereafter, a second metal layer of 9%, for example, Cu or Au, is deposited on the surface of the gold bird film 5 from which the aluminum film has been removed by electroless plating.
It is formed to a thickness of about 1.0 μm. For example, even if the underlying metal layer is difficult to adhere to by electrolytic plating, such as 'I'i, C, there are conditions under which a metal film can be grown by a combination of pretreatment and electroless plating. Thereafter, a metal pant with a thickness of 10 to 20 μm is formed using A11 or Cu1 solder by electrolytic plating using the second metal layer 9 as a plating electrode (FIG. 1(e)). Finally, using the metal bang 10 as a mask, the aluminum oxide layer 8 and the metal layer 5 are removed using their respective etching solutions. In the present invention, one metal layer is entirely formed under the metal bang in a self-aligned manner with respect to the aluminum oxide layer using an electroless plating method. Therefore, since it relies on a strong acid or strong base using the metal bump as a mask, the conventional problem of the wiring aluminum etc. being etched due to seepage of the etching solution is greatly reduced. Furthermore, even if the same material as the metal bump is used for the metal layer formed in a self-aligned manner with respect to the aluminum oxide layer, there is no need to remove this metal layer by etching, so the metal bump can be removed by etching. Fear will disappear.

なお、上記の実施例では、パッド電極上に金属バンプ全
形成するものを示したが、必ずしもパッド電極上でなく
ても、この製造方法を適用できることはいうまでもない
In the above embodiment, the metal bumps are entirely formed on the pad electrode, but it goes without saying that this manufacturing method can be applied even if the metal bumps are not necessarily formed on the pad electrode.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、陽極酸化法による酸化ア
ルミニウム膜をマスクとして用いて無電解メッキ法で後
工程の電解メッキ時に共通電極として用いる金属ノー?
形成し%伏いて同じ酸化アルミニウム膜?マスクに用い
て、電解メ・ツキ法にょ多金属バンプを形成する。金属
バンプを形成した後、エツチングのしやすい酸化アルミ
ニウム膜と、下地の金属層全エツチング除去することに
よシ、従来の多層の金属層を順次エツチング除去するこ
とによるエツチング液のしみこみによる配線アルミニウ
ムのやられ、また金属バングと同じ金属をエツチングし
なけれはならない場合の金属バングの形状の変化を防止
できる利点を有する。
As explained above, the present invention uses a metal no.
The same aluminum oxide film that forms and lies down? Using this as a mask, multi-metal bumps are formed using the electroplating method. After forming a metal bump, the aluminum oxide film, which is easy to etch, and the underlying metal layer are all removed by etching.In contrast, conventional multi-layered metal layers are sequentially etched away and the wiring aluminum is removed by seepage of the etching solution. This has the advantage of preventing changes in the shape of the metal bang when the same metal as the metal bang must be etched.

また無電解メッキ法では、高温でのメッキが必要なため
感光性樹脂膜では耐えきれない温度でも陽極酸化法(よ
る酸化アルミニウム膜をメッキマスクとすることによシ
選択的に無電解メッキが可能となる。
In addition, electroless plating requires plating at high temperatures, so selective electroless plating is possible even at temperatures that photosensitive resin films cannot withstand by using anodized aluminum oxide film as a plating mask. becomes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(flは本発明の一実施例の工程順縦断
面図%第2図[al〜(dlは従来の製造方法の一例を
示す工程順縦断面図である。 1.21・・・・・・半導体基板、2,22・川・・第
1の絶縁膜、3,23・・・・・・アルミパッド電極、
4.24・・・・・・第2の絶縁膜、5,9,26,2
7・・・・・・金属層、6・・・・・・アルミニウム層
、7.28・・・・・・感光性樹脂膜、8・・・・・・
酸化アルミニウム層、10.30・・・・・・金属バン
プ、25・・・・・・電極数シ出し用開孔。 29・・・・・・金属バンプ形成部の開孔。 第 / 回
1.21 FIG. ... Semiconductor substrate, 2, 22... First insulating film, 3, 23... Aluminum pad electrode,
4.24... Second insulating film, 5, 9, 26, 2
7...Metal layer, 6...Aluminum layer, 7.28...Photosensitive resin film, 8...
Aluminum oxide layer, 10.30... Metal bump, 25... Hole for exposing the number of electrodes. 29...Opening of metal bump forming part. th/time

Claims (1)

【特許請求の範囲】[Claims]  半導体基体の一主面に形成された第1の絶縁膜上に所
定形状の金属電極を形成する工程と、前記金属電極に接
して全面に第2の絶縁膜を形成しその所定領域に前記金
属電極上面に通ずる開孔を形成する工程と、前記開孔を
ふくむ前記第2の絶縁膜上に第1の金属層とアルミニウ
ム層を順次積層形成する工程と、前記アルミニウム層の
うち前記金属電極上の所定領域以外を陽極酸化法を用い
て全て酸化アルミニウム層に変える工程と、前記所定領
域のアルミニウム層を蝕刻除去し前記第1の金属層を露
出せしめる工程と、露出した前記第1の金属層上に無電
解メッキ法により第2の金属層を形成する工程と、前記
第2の金属層をメッキ電極として電解メッキ法により前
記第2の金属層に接して第3の金属層を形成する工程と
、前記第3の金属層をマスクとして前記酸化アルミニウ
ム層及び第1の金属層を蝕刻除去する工程を含むことを
特徴とする半導体装置の製造方法。
forming a metal electrode in a predetermined shape on a first insulating film formed on one main surface of a semiconductor substrate; forming a second insulating film on the entire surface in contact with the metal electrode; and forming a second insulating film on the entire surface in contact with the metal electrode; a step of forming an opening communicating with the upper surface of the electrode; a step of sequentially laminating a first metal layer and an aluminum layer on the second insulating film including the opening; a step of converting all areas other than a predetermined region into an aluminum oxide layer using an anodizing method; a step of etching away the aluminum layer in the predetermined region to expose the first metal layer; and a step of exposing the first metal layer. a step of forming a second metal layer thereon by electroless plating, and a step of forming a third metal layer in contact with the second metal layer by electroplating using the second metal layer as a plating electrode. and a step of etching away the aluminum oxide layer and the first metal layer using the third metal layer as a mask.
JP61019411A 1986-01-30 1986-01-30 Manufacture of semiconductor device Pending JPS62177946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61019411A JPS62177946A (en) 1986-01-30 1986-01-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61019411A JPS62177946A (en) 1986-01-30 1986-01-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62177946A true JPS62177946A (en) 1987-08-04

Family

ID=11998509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61019411A Pending JPS62177946A (en) 1986-01-30 1986-01-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62177946A (en)

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