JPS62172740A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To enhance insulating capability by a method wherein a first layer metal wiring is formed on an IC substrate, an insulating film is built by CVD and reactive ion etching to cover only the side walls of the first layer metal wiring, and an insulating film is formed by bias spattering to cover the entire surface. CONSTITUTION:A metal wiring 12 made of an Al-Si alloy is formed on an IC substrate 11 and, on the entire surface including the metal wiring 12, a PSG film 13 is formed by CVD. A process follows wherein reactive ion etching is performed for the etching of the PSG film 13, which continues against its entire surface until there is no PSG film 13 remaining on the horizontal surface of the IC substrate 11. After this process, some PSG film 13 is retained as side walls 13a on the sides of the metal wiring 12. Next, on the entire surface including the metal wiring 12 provided with the side walls 13a, an SiO2 film 14 is deposited by bias spattering. Another metal wiring is then formed on the SiO2 film 14. This method prevents the shoulders of the first metal wiring from exposure and improves the surface geometry of steps to be produced over the first metal wiring 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming multilayer wiring in a semiconductor device, and particularly to a method for forming an interlayer insulating film.

(Prior Art) Conventionally, in a semiconductor device, methods for forming an interlayer insulating film when forming a multilayer wiring include a bias drop four-tuttering method and a method in which CVD is performed after forming a sidewall.

FIG. 2 shows the steps of the bias sputtering method. First, a metal for wiring (for example, M) is vapor-deposited on the IC substrate 1 by a sifter method or the like, and then photolithography and etching are performed to form the first layer metal wiring 2 (FIG. 2(a)). Next, an interlayer insulating film 3 (for example, 810) is formed by bias sputtering under appropriate conditions (see FIG. 2(b)).
)).

FIG. 3 shows the steps of another conventional method in which CVD is performed after forming a sidewall. First, the second
The first layer metal wiring 2 is placed on the IC board 1 in the same manner as in the method shown in the figure.
(Fig. 3(a)).

Next, an insulating film 4 (for example, PSG) is formed by CVD (FIG. 3(b)), and then the insulating film 4 is etched by reactive ion etching until the insulating film 4 on the horizontal surface of the IC substrate 1 is completely removed. do. At this time, due to the characteristics of reactive ion etching, the insulating film 4 on the horizontal plane is removed by etching, but the insulating film 4 is removed along the side surfaces of the first layer metal wiring 2, although the film thickness is slightly reduced.
remains as the sidewall 4a (FIG. 3(c)). Finally, the insulating film 5 is formed once again by CVD (FIG. 3(d)).

(Problems to be Solved by the Invention) However, as shown in circle 6 in FIG. Otherwise, there is a drawback that the same portion is exposed and the first layer metal wiring 2 and the second layer metal wiring 7 are short-circuited.

In addition, in the method of performing CVD after forming the sidewall, as shown in FIG. 5, sufficient flatness cannot be obtained for the insulating film 5 (interlayer insulating film), and the insulating film shown in circle 8 in the figure 5(
There is a drawback that the second layer metal wiring 7 is broken at the stepped portion of the interlayer insulating film.

This invention eliminates the drawbacks of the short between the eyebrows that occurs in the bias 9-tuttering method described above and the disconnection of the second layer metal wiring that occurs in the method of performing CVD after forming the sidewall, and provides excellent insulation and flatness. An object of the present invention is to provide a method for forming a multilayer interconnection having an interlayer insulating film structure.

(Means for Solving the Problems) In the present invention, after forming a first layer metal wiring on an IC substrate, a side wall of an insulating film is formed only on the side surface of the first layer metal wiring by CVD and reactive ion etching. After that, an insulating film is formed on the entire surface by bias sputtering method.

(Function) In this method, the sidewall of the insulating film is damaged, the insulating film is insufficient in the shoulder part of the first layer metal wiring, which was a drawback of the glabella insulating film by bias sputtering, or the insulating film in the same part is removed. Exposure is avoided. Further, after forming the sidewalls, an insulating film is formed on the entire surface by bias sputtering, thereby improving the surface level difference.

(Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

First, a first layer metal wiring 12 made of PHT-81 alloy is formed to a thickness of about 6000λ on an IC substrate 11 by a conventional method (FIG. 1(a)).

Subsequently, a PSG film 13 having a thickness of about 5000 to 7000 mm is formed on the entire surface of the IC substrate 11 including the first layer metal wiring 12 by CVD (FIG. 1(b)).

Next, by reactive ion etching, this P
The SG film 13 is attached to the PSGI [13
Etch the entire surface until it disappears (etching conditions are C* F6/CHFI = 74/16 SCCM
.

600mTorr, 2KW, rate 800A/
(about min).

At this time, due to the characteristics of reactive ion etching,
The PSG film 13 on the horizontal surface of the IC substrate 11 is removed by etching, but the PSG film 13 remains as a sidewall 13a along the side surface of the first layer metal wiring 12, although the film thickness is somewhat reduced (see FIG. 1(c). )).

After the sidewall 13at- of the PSG film (insulating film) is formed in this way, the entire surface of the IC substrate 11 including the first layer metal wiring 12 having the sidewall 13a is re-formed. S/IF ivy rate is 20-4
A Sing film 14 (insulating film) having a thickness of about 10,000^ is deposited by performing bias scattering under the condition of 0%. Here, the conditions for the res/center ratio to be 20 to 40% are as follows: In the case of the device used here, the source side has an 8-inch diameter electrode and the source power is IKW, and the substrate side has a 10-inch diameter electrode and the substrate voltage is -200v~-300V
, the atmosphere was Ar and 0.4 Pa. However, these A? The parameters are highly dependent on the device configuration.

Thereafter, although not shown, a second layer metal wiring is formed on the StO film 14.

(Effect of the invention) As explained in detail above, according to the method of this invention,
By forming a P-wall of an insulating film on the side surface of the first layer metal wiring, the lack of insulation film at the shoulder part of the first layer metal wiring, which was a drawback of the interlayer insulation film using the Bias I Tsuttering method, or , exposure of the same area can be avoided,
It can be expected to improve insulation properties. Therefore, interlayer short circuits can be eliminated. In addition, since the insulating film was formed on the entire surface by the bias snow splattering method after forming the sidewall, the surface level difference, which was a drawback of the method of performing CVD after forming the sidewall, was greatly improved, and the disconnection of the second layer metal wiring was improved. It can be expected to have the effect of suppressing

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the method for forming a multilayer wiring according to the present invention, FIGS. 2 and 3 are process sectional views showing a conventional method, and FIGS. FIG. 3 is a sectional view for explaining the drawbacks of the method. 11... IC board, 12... First layer metal wiring, 13
...PSG film, 13a...side wall, 14.
...Sin. Membrane O Figure 1 $// It's a latte! ['f@Kakuchi Figure 2 Figure 3

Claims (1)

[Scope of Claims] (a) A step of forming a first layer metal wiring on an IC substrate; (b) After that, an insulating film is formed only on the side surface of the first layer metal wiring by CVD and reactive ion etching. (c) Thereafter, a step of forming an insulating film on the entire surface of the substrate including on the first layer metal wiring by a bias sputtering method; (d) the insulating film. 1. A method for forming a multilayer wiring, comprising the step of forming a second layer metal wiring thereon.