JPS62171220A - Buffer circuit - Google Patents

Abstract

PURPOSE:To improve the leading speed and the trailing speed of an input signal independently of slow/fast leading and trailing speed of the input signal by selecting and outputting an output signal on an inverter having two threshold values depending on the set state of a flip-flop. CONSTITUTION:The 1st inverter 1 inverts an input signal Vin at the 1st threshold value VT1 and outputs the result, and the 2nd inverter 2 inverts the input signal Vin at the 2nd threshold value VT2 (<VT1) and outputs the result. A NAND gate 3 sets a flip-flop 7 when both the signals INV1, INV2 are at 'H' level. On the other hand, a NOR gate 4 is reset when at least one of the signals INV1, INV2 is at 'H' level. Since the delay time of circuit components is not utilized as a conventional circuit, the repeating frequency of the input signal is improved, the circuit design is facilitated and the margin to the variance of manufacture is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a buffer circuit that increases the rising speed and falling speed of an input signal and outputs the signal to the outside.

[Prior Art] Conventionally, as a circuit that converts an input signal with a slow rise speed or fall speed into a fast signal and outputs it to the outside, a threshold value is used, as shown in Japanese Patent Laid-Open No. 60-51024, for example. A combination of two inverters with different values and N-channel and P-channel transistors connected complementary to each other, the threshold value of the transistor is determined by the output signal of one of the two inverters at the rise and fall of the input signal: Samurai and There is a high speed inverter circuit that switches dynamically.

[Problem to be Solved by the Invention 1] However, in the above-mentioned high-speed inverter circuit, the threshold values of the transistors are switched by delaying the output inversion time of the inverter that switches the threshold values of the P-channel and N-channel transistors. If the rising or falling speed of the input signal is too fast, or if the capacitive load connected to the output terminal is too large, the output signal will become “H”.
There is a problem in that the output signal of the inverter that switches the threshold value is inverted before it is determined to the II level or the "L" level, and the rising speed and falling speed become "lower". When a capacitor is added to further adjust the output inversion time, there is a problem in that the repetition frequency of the input signal is limited.

The present invention has been made in view of these problems, and an object of the present invention is to provide a buffer circuit that can reliably improve the rising and falling speed of an input signal and output it, and also improve the repetition frequency. It is an object.

[Means for Solving the Problems] The present invention provides a first inverter that inverts an input signal at a first threshold and outputs the inverted signal, and a second inverter that inverts an input signal at a second threshold and outputs the inverter. and a selector that selects one of the output signals of the first and second inverters and outputs it to the outside, and is set to a set state by the output signal of the second inverter, and reset by the output signal of the first inverter. and a flip-flop that controls the selector so that the output signal of the second inverter is output to the outside in the set state and the output signal of the first inverter is output to the outside in the reset state.

[Operation] When the input signal rises, the flip-flop is set by the output signal of the second inverter, and the output signal of the second inverter with the lower threshold is selected by the selector and output. Further, when the input signal falls, the flip-flop is reset by the output signal of the first inverter, and the output signal of the first inverter having a higher threshold is selected by the selector and output.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an input/output signal waveform diagram of each part.

In these figures, the first inverter 1 receives an input signal V
in is inverted by the first threshold value VTI and outputted, and the second inverter 2 inverts the input signal Vin by the second threshold value VT2 (<
VTI) and output it.

Here, the threshold values VT1 and VH2 are set in the relationship of 0<VH2<VDD/2<VTl<VDD, where the power supply voltage is VDD.

Therefore, when the input signal ■in rises, the output signal INV2 of the second inverter 2 is inverted first as shown in FIG. 2(b), and the output signal INV1 of the first inverter 1 is inverted first.
is inverted with a delay when the input signal Vin becomes sufficiently stable, as shown in FIG. 2(C).

Output signals INVI of these inverters 1 and 2.

INV2 is input to the Nant gate 3 and the NOR gate 4.

The Nant gate 3 outputs a high level signal when both the signals IN1 and INV2 are at the high level.

This (r L 1 level signal is input as the set signal S of the RS flip-flop 7 composed of Nantes gates 5 and 6, and sets the flip-flop 7. On the other hand, the NOR gate 4 inputs the signals l N V 1 and INV2 outputs an "L" level signal when at least one of the signals INVI and INV2 is at the "H" level. This @ signal is inverted by the inverter 8 and becomes the reset signal R of the flip-flop 7. That is, the flip-flop 7 is reset when both are at "L" level.

Therefore, when the input signal Vin rises from the "L" level and reaches the 11 Hl! level as shown in FIG. 2 (a), and then returns to the "L" level again, the input signal Vin When the second threshold value VT2) is reached, the signal INV
2 is reversed to 'L' level.

At this time, the flip-flop 7 is in a set state.

The signal INV2 is input to a selector 12 consisting of AND gates 9 and 10 and a NOR gate 11, and when the flip-flop 7 is set, the selector 12 selects the signal INV2, inverts its polarity, and outputs it. When the flip-flop 7 is resetting, the signal INV
It is configured to select I, invert its polarity, and output it.

Therefore, when only the signal INV2 is inverted to the "L" level, the signal INV2 is selected by the AND gate 9 and outputted to the outside via the NOR gate 11. That is, the output signal of the inverter 2 with the lower threshold value is selected and output to the outside.

Thereafter, when the input signal Vin exceeds the threshold value VT1, the output signal INVI of the other inverter 1 is also inverted to the "'high" level. Therefore, the flip-flop 7 is reset by the reset signal R, and its set output signal Q becomes "L" level as shown in FIG. 2(f).

Therefore, when the input signal V1') starts to fall (below the 7° threshold value VT1), at that point the output signal MINV1 of the inverter 1 first inverts to the "H" level, and the output signal of the flip-flop 7 in the reset state selector 12 by
is selected and output. That is, the input signal V
When in falls, the output signal P of inverter 1 with a high threshold
3IN■1 is selected and output.

After this, when the input signal 71 reaches the threshold value VTI or less,
The output (1) of the other inverter 2 is also inverted to "H'" level, and the flip-flop 7 is returned to the same set state as the initial state by the output signal of the Nant gate 3.

As a result of this operation, the input signal ■ shown in FIG. 2(a)
As shown in the figure (( )), in is output as a signal with fast rising and falling speeds.

In addition, when the signal INV2 is (L H1 level), the signal IN
VI is also always at the ``''Hu level. Conversely, the signal I
When NVI is at “L” level, signal INV2 is also always at I(L) level.
It is at II level. Therefore, as shown in FIG. 3, the Nandt gate 3 can be replaced with an inverter 13 which receives the output signal of the inverter 2. In addition, the Noah gate 4 and the inverter 8 are omitted, and the flip-flop 7
can be configured to be directly reset by the output signal e[NVl of the inverter 1.

[North Gate Effect] As is clear from the above explanation, in the present invention, a flip-flop whose output is inverted depending on the rising and falling edges of the input signal is provided, and the output of the inverter has two different threshold values depending on the set state of this flip-flop. Since the signal is selected and output, the rising speed and falling speed of the input signal can be improved and output regardless of whether the rising speed or falling speed of the input signal is slow or slow.

In addition, since the exposure time of circuit elements is not used as in conventional methods, it is possible to improve the repetition frequency of the input signal, making it easier to design the circuit, and providing more margin against manufacturing variations. This has the effect of increasing the size of

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a circuit diagram showing another embodiment of the present invention. 1...first inverter, 2...second inverter l<-
7...Flip-flop, 12...Selector. b Figure 1

Claims (2)

[Claims] (1) A first inverter that inverts and outputs an input signal at a first threshold; a second inverter that inverts and outputs an input signal at a second threshold; A set state is achieved by a selector that selects one of the output signals and outputs it to the outside, and an output signal from the second inverter, and a reset state is achieved by an output signal from the first inverter, and in the set state, the second inverter and a flip-flop that controls the selector so that the output signal of the first inverter is outputted to the outside in a reset state. (2) The first threshold value is set to a value higher than 1/2 of the power supply voltage, and the second threshold value is set to a value lower than 1/2 of the power supply voltage. The buffer circuit described in (1).