JPH0653430A - Cmos output circuit - Google Patents

Abstract

PURPOSE:To ensure stabilized operation by connecting P-channel and N-channel transistors so that the gate potentials are shifted from each other thereby lowering the peak of noise or charge/discharge current. CONSTITUTION:Resistors 13, 14 are inserted between the gates of P-channel MOS transistors 1, 3 and N-channel MOS transistors 2, 4 constituting a first output inverter and second and subsequent output inverters, respectively. P- channel MOS transistors 21, 22 and N-channel transistors 23, 24 for shifting the gate potential are also connected between the transistors 1, 3, 2, 4. These transistors 21-24 suppresses through current of the output inverters. This constitution lowers peak of charge/discharge current of stray capacitance at each part and ensures stabilized operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a CMOS structure output buffer circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have become higher in density and larger in scale, and in particular in logic circuits, input and output signals tend to increase. As this output signal increases, a large noise is generated due to a large transient current of the charging / discharging current with respect to the stray capacitance of the power supply wiring and the ground wiring, and this noise causes a malfunction of the semiconductor integrated circuit device. In order to reduce the maximum value of this charging / discharging current, it is necessary to increase the change time of the rise and fall of the output signal. FIG. 3 shows an example of a conventional CMOS type output circuit in which such measures are taken.

In FIG. 1, a P-channel MOS transistor (hereinafter abbreviated as PMOS) 1 and an N-channel MO transistor are shown.
S transistor (hereinafter, abbreviated as NMOS) 2
A complementary MOS circuit (hereinafter referred to as CMOS) is configured. The PMOS 9 and the resistor form a first inverter 11 that drives the PMOS 1, and the NMOS 10 and the resistor 8 form a second inverter 12 that drives the NMOS 2. Incidentally, 101 is an input terminal and 102 is an output terminal.

FIG. 4 shows the operation waveform. The output waveform of the first inverter 11, that is, the input waveform G1 of the PMOS1
And the output waveform of the second inverter 12, that is, NMOS2
By separately driving the PMOS 1 and the NMOS 2 with the input waveform G2, the through current can be reduced and the noise generated in the power supply and the ground wiring can be reduced. On the other hand, the resistance 7 of the first inverter 11 and the second inverter 1
By increasing the resistance 8 of 2
The turn-on of MOS1 and NMOS2 is delayed, and the maximum value of the charging / discharging current due to the stray capacitance is reduced.

[0005]

However, if the turn-on of these PMOS1 and NMOS2 is delayed,
There is a problem that the speed becomes slower. In addition, resistance 7
CM consisting of NMOS and resistor 8 consisting of PMOS
Even in the case of the OS type inverter, the problem that the speed becomes slow is the same. An object of the present invention is to provide a CMOS type output circuit in which stable operation is ensured by reducing the maximum value of noise and charge / discharge current without causing such a decrease in speed.

[0006]

SUMMARY OF THE INVENTION The present invention has two or more CMOS type output inverters, and each P-channel MOS transistor and N-channel MOS transistor constituting a first output inverter and a second and subsequent output inverters. A resistor is inserted between the gates of the transistors, and a P-channel MOS transistor and an N-channel MOS transistor for shifting the gate potential are connected between the gates of the transistors.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows a CMOS type output circuit of an embodiment of the present invention. In the figure, 101 is an input terminal, 102 is an output terminal, and between these are a first output inverter composed of PMOS1 and NMOS2, and PMOS3 and NMOS4.
Is connected to the second output inverter. That is,
The drains of the PMOSs 1 and 3 and the drains of the NMOSs 2 and 4 are connected to the output terminal 102 to form a CMOS inverter.

The input terminal 101 is a PMOS 2
1, 22 and the gates of the NMOSs 23, 24. The drain of the PMOS 21 is connected to the drain of the NMOS 24 and the source of the PMOS 22, and further connected to the gate of the PMOS 1, and at the same time, the PMOS is connected via the resistor 13.
3 gate. On the other hand, the drain of the NMOS 23 is connected to the drain of the PMOS 22 and the source of the NMOS 24, further connected to the gate of the NMOS 2, and at the same time connected to the gate of the NMOS 4 via the resistor 14.

The operation of this CMOS type output circuit is performed by the PMO.
The size ratio (W / L, W: gate width, L: gate length) of the PMOS 21 is increased from S22, and the NMOS 24
By increasing the size ratio of the NMOS 23,
The respective output waveforms, that is, the input waveforms G1 and G2 of the PMOS1 and the NMOS2 can be set to the operation waveforms in which the deviations are generated as shown in FIG. This allows PMOS1 and N
A first output inverter composed of MOS2, and a PMOS
It is possible to eliminate the shoot-through current of the second output inverter constituted by 3 and the NMOS 4. On the other hand, since the PMOS 3 and the NMOS 4 of the second output inverter are driven via the resistors 13 and 14, the input waveform is blunted and turn-on becomes large. In other words, the maximum value of charge / discharge current becomes small. However, PMOS1 and NM of the first output inverter
Since no resistor is inserted in OS2, the input waveform is not blunted, and high-speed operation is guaranteed.

Further, the maximum value of the charging / discharging current can be made smaller by making the driving capability of the second output inverter larger than that of the first output inverter. As a result, the transient current during simultaneous output operation can be reduced. Although the first inverter does not delay the input waveform due to the resistance for high speed operation, a resistance may be provided in the gate if high speed operation is not required.

FIG. 2 is a CMOS showing a second embodiment of the present invention.
It is a type output circuit. In this embodiment, PM is added to the circuit of FIG.
The configuration is such that the third inverter composed of the OS 5 and the NMOS 6 is connected, and the resistors 15 and 16 are connected. The resistor 15 is provided between the resistor 13 and the gate of the PMOS 5, and the resistor 16 is provided to reduce the input waveform.
4 and the gate of the NMOS 16 are inserted. In this circuit, since the input waveform of the third output inverter is slower than that of the second output inverter, the turn-on of the third output inverter is larger and the charge / discharge current is smaller than that of the second output inverter. .

[0012]

As described above, according to the present invention, the maximum value of the charging / discharging current is reduced by inserting a resistor between the gates of two or more output inverters and shifting the turn-on time.
In addition, stable operation of the semiconductor integrated circuit can be suppressed by connecting the PMOS and the NMOS between the respective gates to generate a shift in the gate potential and suppress the through current, thereby suppressing noise during simultaneous operation of the semiconductor integrated circuit. Has the effect of guaranteeing.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional CMOS output circuit.

FIG. 4 is a diagram showing a waveform of each part.

[Explanation of symbols]

 1,3,5,9,21,22 PMOS 2,4,6,10,23,24 NMOS 7,8,13-16 resistance

Claims (1)

[Claims] 1. A resistance value is provided between the gates of P-channel MOS transistors and N-channel MOS transistors forming the first output inverter and the second and subsequent output inverters, respectively. A CMOS-type output circuit, characterized in that a P-channel MOS transistor and an N-channel MOS transistor for connecting the gate potentials of the respective transistors are connected to each other while being interposed.