JPS62169245A - Data processing system - Google Patents

Abstract

PURPOSE:To take countermeasures against memory error by fail soft and to improve the operating ratio of a system by causing a system processor to take fine countermeasures corresponding to the attributes of data. CONSTITUTION:A processor 11 sends the address of data to a memory device 14 and an address comparator 16 for the purpose of reading out data from the memory device 14. In parallel with data read, the address of data is compared with a boundary address set preliminarily to a register 15 by the address comparator 16. As the result, a signal (attribute discrimination signal) indicating that the data address is smaller or larger than the boundary address is outputted to a line 20 or 21. If the error of read data is detected by a parity checker 17, an interrupt signal is outputted to a line 22 or 23. The processor 11 receives this interrupt signal to perform the rewrite operation.

Description

[Detailed Description of the Invention] [Summary] The attribute of memory data being used by a processor is identified as belonging to the following attributes, and a signal to that effect is given to an error detection means of the memory, and the error detection means sends a signal to the processor. An error detection signal corresponding to the identification signal is supplied to the processor to cause the processor to perform processing in accordance with the error detection signal. In this way, it becomes possible to cause the processor to take appropriate measures corresponding to the data attribute in which the error has occurred, and it is possible to improve the system operating rate.

[Industrial application field]

The present invention relates to a data processing method, and more specifically, to a data processing method that takes into account the attribute of data that causes the error when a memory error occurs in the error processing mode.

A data processing system is made up of various components, and if an error occurs in any of these components, it will no longer be possible to properly process data according to the normal procedure.

Although the system is configured to take countermeasures against errors that impede normal procedures, there is still room for improvement.

[Conventional technology]

For example, in a system that uses a processor to control a terminal device or the like having a built-in memory with a parity check function, notification of a parity error occurring in the memory space is configured to be performed by an interrupt to the processor. This notification is used even if the memory space is logically divided into the required number of parts, and even if an error occurs in any of them, the data error will be stored there and cause the worst situation. It was just a fail-safe countermeasure that forced the processor to take appropriate countermeasures.

[Problem that the invention seeks to solve]

Therefore, if parity occurs in the work area of a logically divided program, the subsequent program movement may deviate from the normal logic, so stopping the system is not recommended under the conventional technique described above. It is reasonable.

However, even if a parity error occurs in the data in the "display/print data" area, if the data can be rewritten from the system host, the system can be restarted even if the above error is detected. Although there is no need to stop the system, under conventional techniques, if a memory error is detected regardless of the data attributes, the system is uniformly stopped. Therefore, this results in a reduction in system availability.
As a result, the system's operating rate is at a low level.

The present invention was created in view of such problems, and an object of the present invention is to provide a data processing method that can improve the system operating rate by taking countermeasures against memory errors as much as possible in a fail-soft manner. .

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 2 is a memory, in which data having different attributes is stored.

2 is a processor that processes data while using the data in the memory 2;

Reference numeral 3 denotes attribute determining means, which determines what attribute the data when the memory is accessed is and outputs an attribute display signal representing the determination result.

4 is connected to the memory l and the attribute determination means 3, and the memory 1
This error detection means detects errors in data and supplies an error detection signal corresponding to the attribute display signal to the processor l.

[Effect]

The attribute of data accessed to the memory 2 is determined by the attribute determining means 3, and an attribute determining signal generated therefrom is supplied to the error detecting means 4.

On the other hand, the error detection means 4 detects the presence or absence of an error in the data, and when an error is detected, an error detection signal indicating that the error corresponds to the attribute discrimination signal is supplied to the processor 1.

In this way, the error detection signal is supplied to the processor 1 in accordance with the data attributes, so that the processor 1 can take specific countermeasures against memory errors.

[Embodiment] FIG. 2 shows an embodiment of the present invention. In this figure, 1
1 is a processor, 12 and 13 are a data bus and an address bus, which are connected to a memory device 14, and the data bus 12 is connected to one input of an address comparator 16 via a boundary address register 15; Address bus 13 is connected to the other input of address comparator 16.

A parity checker 17 is connected to the memory device 14, which receives a comparison result signal from the address comparator 16 and supplies a parity error interrupt signal 18 corresponding to this comparison result signal to the processor 11.

Next, the operation of this embodiment of the invention will be explained.

For convenience of explanation, it will be assumed that the memory space of the memory device 14 is divided into two by the processor 11, that is, the data written to and read from the memory device consists of two attributes.

It is also assumed that the parity checker 17 performs a parity check on data read from the memory device 14. Before data is written to or read from a memory device, a boundary address is sent from the processor 11 via the data bus 12 to a boundary address register, that is, an address that partitions each memory space portion of the memory space divided into two. 15 cents.

Under such a foreshadowing, in order to read data required by the processor 11 for data processing from the memory device 14, the processor 11 sends the address of the data to the memory device 14 and the address comparator 16 via the address bus 13. send.

As a result, while the data is read in the memory device 14, the address of the data is compared with the boundary address preset in the boundary address register 15 in the address comparator 16. A signal (attribute determination signal) indicating whether the address used for reading is smaller or larger than the boundary address is on the line 20.
or output on 21.

If parity checker 17 outputs a parity error for the read data, parity checker 17 outputs a low address parity error interrupt signal on line 22 or 23 in response to a signal on line 20 or 21 or a low address parity error interrupt signal on line 22 or 23. Sends a parity interrupt signal.

A processor responsive to one of these interrupt signals takes appropriate action in response to that interrupt signal. for example,
If the data that caused the interrupt signal to occur was in the program work area, it would cause the system to stop, but the data that caused the interrupt signal to occur is data that can be rewritten by the host device. For example, if it is display/print data, the interrupt signal is used to cause the processor 11 to perform a rewrite operation, thereby avoiding an immediate system down.

As a result, the normal operation of the system continues if the above-mentioned error occurs.

Note that in the above embodiment, the case where the memory space is divided into two has been described, but the invention is not limited to this, and this means that the application to parity error detection in memory refresh is excluded. It's not a thing. Also, other error detection techniques may be used for error detection.

Furthermore, these should not be interpreted as reasons for excluding the application at the time of writing.

Furthermore, when the processor 11 is subordinate, attribute settings may be determined by its higher-level device.

In short, if the present invention can notify the memory device error detection means of the attribute of the data that caused the error, the purpose of the present invention can be achieved.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to force the system processor to take detailed countermeasures according to data attributes, thereby realizing the availability capability of the system and improving the operating rate of the system. .

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. In Figure 1, 1 is a processor, 2 is memory, 3 is an attribute discrimination means; 4 is an error detection means. In Figure 2, 11 is a processor; 14 is a memory device; 15 is a boundary address register; 16 is an address comparator; 17 is a parity checker. Figure 1 old An embodiment of the present invention Figure 2

Claims (2)

[Claims] (1) In a data processing system in which a processor (1) processes data while using data in a memory (2), it is determined what attribute the data has when the memory (2) is accessed. an attribute discriminating means (3) for outputting an attribute display signal representing the discrimination result; and an attribute discriminating means (3) connected to the memory (2) and the attribute discriminating means (3) for detecting errors in the data on which the attribute discrimination has been performed. , an error detection means (4) for supplying an error detection signal corresponding to the attribute display signal to the processor (1), and causing the processor (1) to carry out processing corresponding to the error detection signal. Processing method. (2) The attribute determination means (3) is actually accessed by the processor (11) and the data attribute storage means (15) that stores each piece of data attribute information stored in the memory device (14). comparing means (1) for comparing the attribute information of the data to be displayed and each data attribute information of the data attribute storage means (15) and outputting the attribute display signal;
6) The data processing method according to claim 1, characterized by comprising: