JPH02133843A - Memory error detecting system - Google Patents

Abstract

PURPOSE:To early recover the error of the memory contents by detecting the occurrence of the error and at the same time holding the address signal value. CONSTITUTION:In the case one of memory chips 3a - 3n has a memory error, an error detecting circuit 7 detects the error and produces an error detection signal. Then an address latch circuit 8 performs a latching operation to latch the address signal (showing a reading address at occurrence of an error) outputted from an address expanding circuit 6. At the same time, the circuit 8 supplies the latched address signal to other circuits of a CPU 1, a decoder, etc., via a gate circuit 9. Thus it is possible to detect the occurrence of a memory error in a simple constitution and also to decide a specific memory chip that is produced an error. Then the error can be early recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory error detection method used in microprocessor systems and the like.

(Prior Art) In a computer system using a microprocessor, when data stored in a memory is read out, the data may differ from the stored data for some reason.

For this reason, in order to prevent incorrect data from being used, such computer systems have traditionally been equipped with an error detection circuit that uses a parity check method, etc., to stop the process being executed when a parity error occurs. The execution is interrupted and displays the occurrence of an error.

However, the error detection circuit provided in such a microprocessor system only determines the presence or absence of an error, but does not provide information effective for subsequent error processing and recovery processing.

For this reason, when an operator handles an error, he or she must check each address in the memory from the beginning to determine where the error has occurred and the content of the error, which poses a problem in that it takes time to recover from the error.

In addition, if the memory error occurs at a rate of about 1 in several thousand times due to performance deterioration due to aging of the circuit, etc., when the operator checks the error location, the memory will operate normally and the error location will be removed. Sometimes I couldn't find it.

(Object of the Invention) The present invention has been made in view of the above-mentioned circumstances, and it is possible to identify the location where a memory error occurs with a simple configuration, thereby enabling early recovery from the error. The purpose is to provide a detection method.

(Summary of the Invention) In order to solve the above problems, in the memory error detection method according to the present invention, when an error occurs in the memory contents read by the microprocessor, this is detected and the address signal value at this time is detected. The feature is that the address where the error occurred can be found later.

(Embodiment) FIG. 1 is a block diagram showing an example of a microprocessor system to which an embodiment of the memory error detection method according to the present invention is applied.

The microprocessor system shown in this figure includes a CPU that is the center of the system, an address decoder 2 that decodes the upper few bits of the address signal output from the CPUI, and generates only one chip select signal C81 to CSn. A memory section that has a plurality of memory chips 38 to 3n, and one of the memory chips is selected by the chip select signal outputted from the address decoder 2 and the remaining bits of the address signal, and the internal address thereof becomes readable and writable. 4, and each of the memory chips 3a to 3n.
The error detection section 5 detects when an error occurs in any one of the address signals and holds the address signal value at that time.

The error detection unit 5 includes an address expansion circuit 6 that expands the address signal output from the CPUI for a predetermined time (for example, the time until the next address signal is output);
Error detection is performed by performing a parity check (or other check) on data signals input and output to each of the memory chips 3a to 3n, and detecting when a memory error occurs in any of the memory chips 3a to 3n. an error detection circuit 7 that generates a signal; and an address expansion circuit 6 when an error detection signal is output from the error detection circuit 7;
The address latch circuit 8 takes in and latches the address signal held by the address latch circuit 8, and the gate circuit 9 supplies the address signal latched by the address latch circuit 8 to other circuits such as the CPUI and the decoder. There is.

When the memory chips 3a to 3n are operating normally, the error detection circuit 7 of the error detection section 5 does not generate an error detection signal, so the address latch circuit 8 does not perform a latch operation.

Furthermore, if a memory error occurs in any of the memory chips 38 to 3n, the error detection circuit 7 detects this and generates an error detection signal. As a result, the address latch circuit 8 performs a latch operation to latch the address signal (address signal indicating the read address when an error occurs) output from the address expansion circuit 6, and also sends the address signal via the gate circuit 9. is supplied to the CPUI and other circuits such as a decoder.

As described above, in this embodiment, the memory chips 3a to
If a memory error occurs in any of 3n, the address signal value at that time is latched, so if you display the contents later as necessary, you can see which part of which memory chip caused the error. This makes it easy to know whether the error is occurring or not, and this allows for early recovery from the error.

(Effects of the Invention) As explained above, according to the present invention, it is possible to detect the occurrence of a memory error with a simple configuration, and it is also possible to determine which memory chip has caused the error. can be restored quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a microprocessor system to which an embodiment of the memory error detection method according to the present invention is applied. 1... Microprocessor (CPU), 3a to 3n
...Memory chip, 5...Error detection section. Patent applicant: Toyo Tsushinki Co., Ltd.

Claims (1)

[Claims] (1) A memory error detection method that detects when an error occurs in data read from a memory by a microprocessor, holds the address signal value at that time, and displays it as necessary.