JPH07200417A - Memory error detection device - Google Patents

Abstract

PURPOSE:To specify the occurrence part of a memory error and replace the memory of the error occurrence part without stopping the whole system. CONSTITUTION:An error check part 200 detects error occurrence as to memory parts 110-140 and an error memory select signal holding part 300 holds memory select signals 710-740 at the time of the error detection. The signals held by the error memory select signal holding part 300 are reported to error display parts 410-440 as error reports 310-340 and also reported to a power supply part 500, and they are used to stop the power supply to the memory where the error occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory error detecting device for detecting an error in a memory and specifying an error portion.

[0002]

2. Description of the Related Art In a conventional memory error detection device, when an error in a memory is detected, it is possible to recognize that an error has occurred in the entire memory, but it is not possible to specify in which part the error has occurred. It was

Referring to FIG. 4, four memories 110 to 110 are provided.
2 is an example of a conventional technique of a memory error detection device that detects the occurrence of an error regarding 140. Each memory 110-14
Address 600 is supplied to 0, and memory selection signal 710
Only one of ~ 740 is enabled. As a result, read data is output from only one of the memories 110 to 140. The error check unit 200 performs an error check on the data on the data line 800 at the timing given by the read data fetch timing 210. If an error has occurred, error report 22
0 is reported to that effect.

[0004]

The above-mentioned conventional memory error detection device only detects an error in the entire memory, and in any memory portion, for example, a memory chip or a group of memory chips has an error. There is a problem that it is difficult to identify whether it has occurred.

[0005]

In order to solve the above-mentioned problems, the present invention is a memory error detecting device for detecting an error occurrence of a memory in a memory device comprising a plurality of memories having a common read data line. Error check means for detecting occurrence of an error in the data on the read data line, and error memory selection signal holding for holding a memory selection signal for each of the plurality of memories when the error occurrence is detected by the error checking means Means and an error display section for displaying the signal held by the error memory selection signal holding means, and specifies in which of the plurality of memories the error has occurred.

Further, it further comprises a power supply control section for instructing to stop the power supply to the memory in which an error has occurred, in response to a signal from the error memory selection signal holding means.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the memory error detecting device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the memory error detecting apparatus according to the first embodiment of the present invention has four memory sections 1.
10 to 140, an error check unit 200 for detecting the occurrence of an error, and any of the memory units 110 to 140
Error memory selection signal holding unit 300 that holds whether an error has occurred, and an error display unit 31 that displays that an error has occurred for each of the memory units 110 to 140.
0 to 340 are included.

Each of the memories 110 to 140 is selected by the memory selection signals 710 to 740, and the address line 6 is selected.
Data is read using the address supplied by 00 and the read data is output to the data line 800.
Here, the memory selection signals 710 to 740 are stored in the memory 11
It is controlled so that only one of 0 to 140 is selected. Therefore, no data is output from the plurality of memories to the data line 800.

Further, the memories 110 to 140 include a code for error detection. When using a parity as a code for this error detection, for example, a configuration is possible in which data of one word is stored in the memories 110 to 130 in 3 bits and 1 bit of parity is stored in the memory 140. At this time, assuming that the data stored in the memories 110 to 140 are D1, D2, D3, and D4, respectively,
D4 is set so that the following equation holds.

D4 = D1 xor D2 xor D3 (1) where xor represents an exclusive OR.

The error checking section 200 fetches the data on the data line 800 at the fetch timing given by the read data fetch timing 210 and checks the occurrence of an error. Error check unit 2
When checking the occurrence of an error, 00 checks whether or not a preset relationship, for example, the relationship represented by the formula (1) is established. If an error is detected, the error detection signal 220 is output to the error memory selection signal holding unit 300.

Upon receiving the error detection signal 220 from the error check unit 200, the error memory selection signal holding unit 300 holds the memory selection signals 710 to 740 input to the memories 110 to 140. As a result, the error report 310 is sent to the corresponding error display sections 410 to 440.
~ 340 can be output.

Next, the operation of the memory error detecting device according to the first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 2, there is shown a timing chart in the memory error detecting device according to the first embodiment of the present invention.

First, at the 0th clock, it is shown that only the memory selection signal 720 of the memory selection signals 710 to 740 becomes valid at the rising edge of the clock. As a result, the memory 2 is selected and data is read from the memory 2 at the address indicated by the address line 600. The read result is output to the data line 800. The read data on this data line 800 is
The error check unit 200 receives the read data at the read timing 210 and becomes an error check target. The result of this error check is output to the error detection signal 220. In the example of FIG. 2, the data from this memory 2 is normal data,
The error detection signal 220 remains in the non-occurrence state.

At the first clock, the input data does not change, and the operation of the memory error detecting device does not change.

Next, at the second clock, it is shown that only the memory selection signal 710 of the memory selection signals 710 to 740 becomes valid at the rising edge of the clock. As a result, the memory 1 is selected and data is read from the memory 1 at the address indicated by the address line 600. The read result is output to the data line 800 as in the case of the 0th clock. This data line 8
The read data on 00 is fetched by the error check unit 200 at the fetch timing from the read data fetch timing 210 and becomes an error check target. This error check result is the error detection signal 220
Is output to. The example of FIG. 2 shows a case where the data from the memory 1 is abnormal, and the error detection signal 2
Reference numeral 20 indicates an error detection state from clock 2 to clock 3.

At the third clock, the error detection signal 220
In response to this, the memory selection signals 710 to 740 are held in the error memory selection signal holding unit 300 due to the rising of the clock. Regarding the states of the memory selection signals 710 to 740 at this time, only the memory selection signal 710 shows a valid state, and the other memory selection signals 720 to 740 show a invalid state. As a result, from the rising edge of the third clock, only the error report 310 shows the valid state, and the other error reports 320 to 340 show the invalid state. That is, only the error report 310 reports the error, and only the error display unit 410 displays the error. Thereby, the operator or the maintenance person can know which of the memories 110 to 140 in which the error has occurred by monitoring the error display sections 410 to 440.

Next, a second embodiment of the memory error detecting apparatus of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, the memory error detecting device according to the second embodiment of the present invention has an operator instruction line 5
It has the same configuration as that of the second embodiment except that a power control unit 500 for inputting 50 is added.

The power control unit 500 includes an error check unit 2
When an error is detected by 00, an error report 310 to 340 is received from the error memory selection signal holding unit 300 to report in which memory the error occurred. Upon receiving this error report, the power supply control unit 500
Stops the power supply to the corresponding memory. The stop of power supply to the memory is instructed by power supply control signals 510 to 540.

With such a configuration, also in the second embodiment, the operator or maintenance person monitors the error display sections 410 to 440 to detect an error in any of the corresponding memories 110 to 140. You can know what happened. Further, in the second embodiment, since the power supply to the memory in which the error has occurred is stopped, the operator or maintenance person can replace the corresponding memory without stopping the entire system.

After the memory is replaced, the operator or maintenance person gives an instruction to restart the power supply by the operator instruction line 550. Accordingly, the power supply unit 500 gives an instruction to restart the power supply through the power control signals 510 to 540, and completes the memory replacement without stopping the entire system.

In the embodiment of the present invention, there are four memories to be subjected to error checking, but it goes without saying that this memory can be constructed by an arbitrary number according to the system requirements.

[0026]

As described above, according to the present invention, by monitoring the error display portion, the operator or maintenance person can easily specify the portion where the error has occurred. Also,
The power supply to the memory in which the error has occurred is automatically stopped, and the operator or maintenance person can replace the corresponding memory without stopping the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory error detection device of the present invention.

FIG. 2 is a diagram showing a timing chart of the operation of the memory error detection device of the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a memory error detection device according to a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a memory error detection device according to a conventional technique.

[Explanation of symbols]

 110-140 memory 200 error check section 210 read data import timing 220 error detection signal 300 error memory selection signal holding section 310-340 error report 410-440 error display section 500 power supply control section 510-540 power supply control signal 550 operator instruction line 600 Address line 710-740 Memory selection signal 800 Data line

Claims (2)

[Claims] 1. A memory error detection device for detecting a memory error occurrence in a storage device comprising a plurality of memories having a common read data line, the error check detecting an error occurrence in data on the read data line. Means, an error memory selection signal holding means for holding a memory selection signal to each of the plurality of memories when an error occurrence is detected by the error checking means, and a signal held by the error memory selection signal holding means And an error display unit for displaying the error, which specifies in which of the plurality of memories the error has occurred. 2. A power supply control unit for instructing to stop power supply to the memory in which an error has occurred, in accordance with a signal from the error memory selection signal holding means. The memory error detection device described in 1.