JPS6214917B2 - - Google Patents
Info
- Publication number
- JPS6214917B2 JPS6214917B2 JP57090161A JP9016182A JPS6214917B2 JP S6214917 B2 JPS6214917 B2 JP S6214917B2 JP 57090161 A JP57090161 A JP 57090161A JP 9016182 A JP9016182 A JP 9016182A JP S6214917 B2 JPS6214917 B2 JP S6214917B2
- Authority
- JP
- Japan
- Prior art keywords
- power
- sequence
- waveform
- bubble memory
- bubble
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0875—Organisation of a plurality of magnetic shift registers
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57090161A JPS58205987A (ja) | 1982-05-27 | 1982-05-27 | バブルメモリ装置の電源シ−ケンス検査方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57090161A JPS58205987A (ja) | 1982-05-27 | 1982-05-27 | バブルメモリ装置の電源シ−ケンス検査方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58205987A JPS58205987A (ja) | 1983-12-01 |
JPS6214917B2 true JPS6214917B2 (enrdf_load_html_response) | 1987-04-04 |
Family
ID=13990763
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57090161A Granted JPS58205987A (ja) | 1982-05-27 | 1982-05-27 | バブルメモリ装置の電源シ−ケンス検査方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58205987A (enrdf_load_html_response) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63143016U (enrdf_load_html_response) * | 1987-03-11 | 1988-09-20 |
-
1982
- 1982-05-27 JP JP57090161A patent/JPS58205987A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63143016U (enrdf_load_html_response) * | 1987-03-11 | 1988-09-20 |
Also Published As
Publication number | Publication date |
---|---|
JPS58205987A (ja) | 1983-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2577120Y2 (ja) | 過剰パルス印加の禁止回路 | |
JP3200009B2 (ja) | 読出電圧と書込電圧とが異なる強誘電性メモリ感知方法 | |
US20080052584A1 (en) | Test apparatus and test method | |
JP2001518625A (ja) | 集積回路テスタのためのフォーマットに感応したタイミング較正 | |
US5481551A (en) | IC element testing device | |
JPS61133873A (ja) | 半導体試験装置 | |
JPS6214917B2 (enrdf_load_html_response) | ||
US6496953B1 (en) | Calibration method and apparatus for correcting pulse width timing errors in integrated circuit testing | |
US3048828A (en) | Memory device | |
US20150262710A1 (en) | Method and system for reducing memory test time utilizing a built-in self-test architecture | |
JP2000090693A (ja) | メモリ試験装置 | |
JPS61280100A (ja) | メモリ試験装置 | |
SU1374278A1 (ru) | Способ записи информации в запоминающее устройство на биаксах | |
JP2831081B2 (ja) | Ic試験装置 | |
SU364030A1 (ru) | Устройство для проверки ферритовых матриц оперативных запоминающих устройств | |
JPS6140574A (ja) | 試験条件設定装置 | |
SU369627A1 (ru) | ^:-с^:союэная | |
JPS57111472A (en) | Logical-circuit testing device | |
JPS5947265B2 (ja) | パタ−ン発生装置 | |
SU1644227A1 (ru) | Устройство дл контрол доменной пам ти | |
JP2846383B2 (ja) | 集積回路試験装置 | |
JPH02231652A (ja) | トレース装置 | |
JPS5837891A (ja) | 磁気バブルメモリデバイス | |
JPH07169299A (ja) | アドレスデータ発生装置 | |
US20030056162A1 (en) | Method for testing a circuit unit to be tested and test apparatus |