JPS62148989U - - Google Patents
Info
- Publication number
- JPS62148989U JPS62148989U JP3542286U JP3542286U JPS62148989U JP S62148989 U JPS62148989 U JP S62148989U JP 3542286 U JP3542286 U JP 3542286U JP 3542286 U JP3542286 U JP 3542286U JP S62148989 U JPS62148989 U JP S62148989U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- utility
- circulation circuits
- model
- resets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000009966 trimming Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Electromechanical Clocks (AREA)
- Electric Clocks (AREA)
Description
第１図ないし第３図はこの考案の一実施例を示
し、第１図は同例の全体回路図、第２図は発振回
路５０、分周回路５１、タイミング発生回路５４
の詳細回路図、第３図は第２図の回路の動作を示
すヨイムチヤート、第４図は従来のトリミング回
路の回路図、第５図は第４図中のラツチ回路の具
体的回路図である。
１１……太陽電池回路、１２，１４……トリミ
ング回路、１７……スイツチ入力回路、１３……
定電圧回路、１５……時計回路、１６……表示回
路。
1 to 3 show an embodiment of this invention, FIG. 1 is an overall circuit diagram of the same example, and FIG. 2 shows an oscillation circuit 50, a frequency dividing circuit 51, and a timing generation circuit 54.
3 is a diagram showing the operation of the circuit in FIG. 2, FIG. 4 is a circuit diagram of a conventional trimming circuit, and FIG. 5 is a specific circuit diagram of the latch circuit in FIG. 4. . 11... Solar cell circuit, 12, 14... Trimming circuit, 17... Switch input circuit, 13...
Constant voltage circuit, 15... Clock circuit, 16... Display circuit.
Claims (1)
ト、インバータから成る複数の循環回路と、 これら複数の循環回路を夫々異なるタイミング
でリセツトするタイミング信号発生回路 とから成ることを特徴とする入力回路。[Claims for Utility Model Registration] A utility model consisting of a plurality of circulation circuits each consisting of a NOR gate and an inverter connected to a predetermined input terminal, and a timing signal generation circuit that resets the plurality of circulation circuits at different timings. Characteristic input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3542286U JPS62148989U (en) | 1986-03-13 | 1986-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3542286U JPS62148989U (en) | 1986-03-13 | 1986-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62148989U true JPS62148989U (en) | 1987-09-21 |
Family
ID=30844898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3542286U Pending JPS62148989U (en) | 1986-03-13 | 1986-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62148989U (en) |
-
1986
- 1986-03-13 JP JP3542286U patent/JPS62148989U/ja active Pending