JPS62144342A - Forming method of contact hole for multilayer interconnection - Google Patents

Abstract

PURPOSE:To round the edge section of a via hole, to remove a disconnection at the step of a wiring and to obtain a contact hole for a multilayer interconnection having excellent coatability at the step and high reliability by using a plasma Si3N4 film formed at room temperature as a hard mask material and adding heat treatment after the patterning of a hard mask. CONSTITUTION:A conductor 12 is patterned on a lower base 11, an insulating film 13 consisting of an organic resin film is shaped onto the conductor 12, and a hard mask 14 composed of an Si3N4 film formed at room temperature is shaped onto the insulating film 13. A resist pattern 15 is formed onto the hard mask 14 and the hard mask 14 is patterned, and the hard mask 14 and the insulating film 13 are thermally treated. Dry etching is conducted in an isotropic manner through reactive ion etching in an O2 gas atmosphere. The hard mask 14 is removed through a method such as a dry etching method, and a contact hole for a multilayer interconnection is formed. Second layer aluminum 17 is deposited in the contact hole. Accordingly, a via hole, an edge section thereof is rounded, can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming contact holes in multilayer wiring in the manufacture of LSIs, and particularly to a method for forming bayer holes.

(Prior art) Conventionally, there are wet etching methods, dry etching methods, etc. in the formation process of LSI multilayer interconnections using organic resin films, but in particular, the tri-etching method is called RIB (reactive ion etching). Because it uses active ion enoching technology, it is suitable for forming fine patterns.

The process of forming multilayer wiring using this dry etching method is as follows:
Conventionally, this has been carried out by a method as shown in FIG.

(1) First, as shown in FIG. 2(a), the first I! Form the third aluminum pattern 2.

(2) Next, as shown in FIG. 2(b), an organic thin film 3 is formed.

(3) Next, as shown in FIG. 2(c), a hard mask 4 is formed.

(4) Next, a resist is applied and a resist pattern 5 is formed by lithography as shown in FIG. 2(d).
form.

(5) Next, as shown in FIG. 2(e), the hard mask 4 is patterned.

(6) Next, as shown in FIG. 2(f), the resist pattern 5 is removed.

(7) Next, as shown in Figure 2 (g),
Patterning of the film 3 is performed.

(8) Next, as shown in FIG. 2(h), the hard mask 4 is removed.

(9) Then, as shown in FIG. 2(i), a second layer of aluminum 6 is deposited.

In addition, when removing the hard mask in (8) above, the hard mask is used as an etching mask to transfer the resist pattern to the organic thin film, and the materials used include aluminum, plasma Si 3N 4, and SOG (spin-on film). (on glass) etc. are used.

Further, the RIE method is used for patterning the hard mask in (5) above and patterning the organic thin film in (7) above, making it possible to form fine patterns of 3 μm or less. For patterning hard masks, a gas suitable for each material is used, and for patterning organic thin films, Oz gas or CF gas is usually used.

(Problems to be Solved by the Invention) However, the shape of the Bayer hole formed by the above method is very steep because RIE is used, and in particular, the shape of the Bayer hole formed by the above method is very steep as shown in FIG. As you can see, the edges are angular. When a second layer of aluminum is formed by sputtering in this state, the second layer of aluminum is formed by sputtering.
As shown in Figure (i), there was a problem in that the aluminum became thinner at the edges, making it easy for the wiring to break.

The present invention eliminates the above problems and improves the construction of the buyer hall.
It is an object of the present invention to provide a method for forming a contact ball in a multilayer wiring which has rounded edges, eliminates step breaks in the wiring, and has good step coverage and high reliability.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention uses a plasma Si3N4 film formed at room temperature as a heart mask material in a contact hole forming method for multilayer wiring, and also uses a plasma Si3N4 film formed at room temperature as a heart mask material. After the patterning step, a high temperature beta treatment is added, and the pressure is set to 20 to 30 Pa when patterning the J113 film, thereby reducing the anisotropic component during etching.

(Function) According to the present invention, in a method for forming a contact hole in a multilayer wiring, a plasma S1:IN4 film formed at room temperature is used as a hard mask material, and a high temperature beta treatment is added after the hard mask patterning step. Furthermore, by applying a pressure of 20 to 30 Pa when patterning the organic thin film, the anisotropic component is reduced during etching, so that a higher-order shape with rounded edges can be obtained. Therefore, it is possible to form a contact hole for a multilayer interconnection with good step coverage and high reliability.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Here, an example of the present invention will be described based on an example using a polyimide organic resin film.

(1) First, as shown in FIG. 1(a), a first layer of aluminum pattern 12 is formed on the lower substrate 11.

(2) Next, as shown in FIG. 1(b), a thin polyimide organic resin film 13, for example, 1 μm thick, is formed. The curing heat treatment at this time is carried out in several stages, with the final stage being carried out at 350°C for at least 1 hour.

(3) Next, as shown in FIG. 1(c), plasma 3 i 3N a is formed at room temperature as a hard mask.
A film 14 with a thickness of 0.3 μm is formed. The formation conditions are, for example, approximately 24° C., RF power 0.1 to 0.2 W/am”
, using gas SHH-/NHi/Nz, the flow rate ratio is 1
:2-3:11-12 at a pressure of 100-200 Pa.

(4) Next, a resist is applied, and as shown in FIG. 1(d), a resist pattern 1 is formed by lithography.
form 5.

(5) Next, as shown in FIG. 1(e), the plasma Si 3 N 4 film 14 is etched. In this case, the gases used are C2F6 and CHFI or CF,
Etching is performed using a dry etching method.

(6) Next, as shown in FIG. 1(f), the resist pattern 15 on the hard mask 14 is removed by a surfactant solution or acetone ultrasonic treatment.

(6) Next, heat treatment is performed as shown in FIG. 1(g). This 4-tone treatment is carried out at 100 to 200°C for 5 to 10 minutes.

(7) Next, as shown in FIG. 1(h), the polyimide organic resin film 13 is etched by the l'lE method using 0□ plasma. Here, for example, the pressure is 20
~30P a, RF power 0.05-0.2 W/
Do it with aA.

(8) Finally, as shown in FIG. 1(i), the hard mask 14 is removed by a tri-etching method using C2F6 and CHF or CF.

In this way, contact holes for multilayer wiring are formed. Then, in this contact hole, as shown in Fig. 1 (j)
A second layer of aluminum 17 is deposited as shown in FIG.

Here, the characteristic points of the present invention and their effects will be explained.

Import') S, N, membranes are organic IJi like polyimide resin membranes.
The coefficient of thermal expansion is significantly different from that of That is, the polyimide resin film has a temperature of 20 to 70 cal/cm, see, °C, whereas the St's Na film has a temperature of 2.8 to 3.2
cal/cm, sec, 'c. Therefore,
When heat treatment is performed on a film with a two-layer structure of a polyimide resin film and an S r 3 Na film, the polyimide resin film and s+, N
As a result, a minute gap 16 is generated between the polyimide resin film at the patterning edge portion and the St+N4 film. After creating such a gap, RIE is performed in an 02 atmosphere, but at that time, a relatively high pressure is applied such that the anisotropic component of the etching species is small, for example,
When etching is performed under a pressure of 20 to 30 Pa, the etching species enters the minute gap described above and etches the polyimide resin film in the direction of widening the minute gap.

(ii) Plasma S formed at room temperature as a hard mask
The reason for using the i 3 Na film is as follows.

Conditions for etching the organic resin film, e.g. RF
Power 0.5 1.5W/cI11. Pressure 5-20Pa
, when etching with 02 gas, the temperature of the cavity was approximately 300°C.
3,3N, film formed at room temperature than Si z N
The etching rate is faster for the 4-layer film. For this reason, in the process of expanding the minute gap described above, s, N, lI! formed at room temperature! If you use , the gap will expand towards the hard mask side faster. For that purpose, st3Nml formed at room temperature! When J is used, the etching species can more easily reach the minute gaps, thereby making it easier for the edges to become rounded.

With this configuration, a bayer pole with rounded edges can be formed.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, (a)
(b) forming a hard mask made of a Si 3 N 1 film formed at room temperature on the insulating film; , (c) forming a resist pattern on the cough heart mask and patterning the heart mask; (d) performing heat treatment on the insulating film and (e) applying 02 gas. By using an isotropic trial etching process using reactive ion etching in an atmosphere, the shape of the Bayer hole in a multilayer wiring structure has been changed from the traditional angular shape with steep edges to a shape with sharp edges. It can be made into a round shape with good step coverage.

Therefore, when depositing the second layer of aluminum, breakage at the edge of the bayer hole can be prevented.

In this way, the step coverage of the multilayer wiring can be improved, so that the reliability of the wiring in LSI manufacturing can be improved.

Moreover, it is applicable not only to Bayer holes between the first and second layers, but also to Bayer holes between layers in multilayer wiring of three or more layers.

[Brief explanation of drawings]

FIG. 1 is a process diagram for forming a contact hole in a multilayer wiring according to the present invention, and FIG. 2 is a process diagram for forming a contact hole in a conventional multilayer wiring. 11... Lower substrate, 12... First layer aluminum pattern, 13... Thin polyimide organic resin film, 14... Room temperature formation plasma S i 3 N h
Film, 15...Resist pattern, 16...Gap, 1
7... Second layer of aluminum. Patent applicant Oki Electric Industry Co., Ltd. Representative Patent attorney Shimizu 9 Figure 1
) Figure 1 (Part 2) Figure 2 (Text No. 7) Figure 2 Part 2)

Claims (3)

[Claims] (1) (a) Step of patterning a conductor on the lower substrate and forming an insulating film made of an organic resin film thereon; (b) Forming a hard mask made of a Si_3N_4 film formed at room temperature on the insulating film. (c) forming a resist pattern on the hard mask;
A step of patterning the hard mask, (d) a step of heat-treating the hard mask and the insulating film, and (e) a step of performing isotropic dry etching by reactive ion etching in an O_2 gas atmosphere are sequentially performed. 1. A method for forming contact holes in multilayer wiring, characterized in that: (2) The heat treatment in the step (d) above is performed at a temperature of 100 to 2
2. A method for forming a contact hole in a multilayer wiring according to claim 1, wherein the contact hole forming method is performed at a temperature of 0.000°C. (3) The etching in the step (d) is 20 to 3
2. A method for forming a contact hole in a multilayer wiring according to claim 1, wherein the method is performed in an atmosphere of 0 Pa.