JPS6232609A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6232609A
JPS6232609A JP17187985A JP17187985A JPS6232609A JP S6232609 A JPS6232609 A JP S6232609A JP 17187985 A JP17187985 A JP 17187985A JP 17187985 A JP17187985 A JP 17187985A JP S6232609 A JPS6232609 A JP S6232609A
Authority
JP
Japan
Prior art keywords
film
aluminum
photoresist
aluminum wiring
sputtered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17187985A
Other languages
Japanese (ja)
Inventor
Tetsuo Higuchi
哲夫 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17187985A priority Critical patent/JPS6232609A/en
Publication of JPS6232609A publication Critical patent/JPS6232609A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an aluminum wiring whose dimensional shift from a resist pattern is minimized by using an aluminum film and an SiO2 or Si3N4 film having more excellent adhesion as a mask and then by etching the aluminum film. CONSTITUTION:After a contact hole 4 is formed, the aluminum film 6 is sputtered on the entire surface of a wafer and then an insulating film 8 made of an SiO2 or Si3N4 film is sputtered. Next, aluminum wiring patterning is performed by using a photoresist 7 and then the insulating film 8 made of an SiO2 or Si3N4 film is etched using Freon gas by making this photoresist 7 as a mask. After this, the aluminum film 6 is etched by using phosphoric acid or chlorine gas. Finally, the aluminum wiring 6 is formed by removing the photoresist 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ホトマスクから転写されたレジストパター
ンからの寸法シフトを最小限に押さえた金属配線の形成
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming metal wiring in which dimensional shift from a resist pattern transferred from a photomask is minimized.

〔従来の技術〕[Conventional technology]

従来、半導体素子にアルミニューム配線を形成する方法
としては第2図および第3図に示す工程があった。両図
において、(りはエピタキシャル層、(2ンはベース拡
散層、(3丹まエミッタ拡散層、(4)はコンタクト孔
、(5)は酸化膜、(6)はスパッタアルミニューム膜
、(7)はパターニングされたホトレジストである。
Conventionally, there have been steps shown in FIGS. 2 and 3 as a method for forming aluminum wiring in a semiconductor element. In both figures, (ri is an epitaxial layer, (2) is a base diffusion layer, (3 is an emitter diffusion layer, (4) is a contact hole, (5) is an oxide film, (6) is a sputtered aluminum film, ( 7) is a patterned photoresist.

次に、従来のアルミニュームエツチング法について説明
する。まず、第2図(a)に示すようK、コンタクト孔
(4)の開口後、全面にアルミニューム(6)をスパッ
タし、そしてホトレジスト(7)にてアルミニューム配
線のパターニングを行う。次に、申)図のようにホトレ
ジスト(7)をマスク忙してアルミニューム膜(6)を
りん酸などのエツチング液でエツチングする。ついで、
ホトレジスト膜(7)を除去してアルミニューム配線(
6)の形成工程が完了する(0図参照)。
Next, a conventional aluminum etching method will be explained. First, as shown in FIG. 2(a), after opening a contact hole (4), aluminum (6) is sputtered over the entire surface, and aluminum wiring is patterned using photoresist (7). Next, as shown in the figure, the aluminum film (6) is etched with an etching solution such as phosphoric acid while masking the photoresist (7). Then,
The photoresist film (7) is removed and the aluminum wiring (
The formation step 6) is completed (see Figure 0).

同様に第3図(a)〜(C)は、ホトレジスト(7)を
マスクにし、そして塩素系のガス等を用いてアルミニュ
ーム配線(句のドライエツチングを行5工程を示したも
のである。
Similarly, FIGS. 3A to 3C show the 5th step of dry etching aluminum wiring using a photoresist (7) as a mask and using chlorine gas or the like.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のアルミニューム配線のエツチング法は、以上のよ
うにスパッタアルミニューム膜(6)と密着性の悪いホ
トレジスト(7)をマスクとしているため、第2図のよ
うにりん酸を用いたウェットエツチングでは、アルミニ
ューム膜(6)のサイドエッチ量6υが大きくなり、し
たがって、アルミニューム配線(6)の幅が狭(なって
しまう。また、第6図のように塩素系ガスを用いたドラ
イエツチングでは、レジスト端σDが後退しながらエツ
チングが進行するため、アルミニューム配線(6)の仕
上がり寸法は狭くなるという欠点があった。
The conventional etching method for aluminum wiring uses the sputtered aluminum film (6) and the photoresist (7), which has poor adhesion, as a mask as described above, so wet etching using phosphoric acid as shown in Fig. 2 is difficult. , the side etching amount 6υ of the aluminum film (6) becomes large, and the width of the aluminum wiring (6) becomes narrower.Also, as shown in Fig. 6, dry etching using chlorine gas Since etching progresses while the resist edge σD recedes, there is a drawback that the finished dimension of the aluminum wiring (6) becomes narrower.

〔問題点を解決するための手段〕[Means for solving problems]

この発明は、上記のような従来方法による欠点を除去す
るためになされたもので、アルミニューム膜の全面スパ
ッタ後、その上に酸化膜(Sin2)あるいは窒化膜(
Si3N4)の絶縁膜をスパッタし、そしてホトレジス
トでアルミニューム配線のパターニングを前記の(Si
O2)膜、あるいは(SisN4)膜上に行うもので、
アルミニューム膜と密着性の良い(Si02)膜または
(Si3N4)膜の絶縁膜をマスクにして、前記アルミ
ニューム膜のエツチングを行なったものである。
This invention was made in order to eliminate the drawbacks of the conventional method as described above. After sputtering the entire surface of an aluminum film, an oxide film (Sin2) or a nitride film (
Sputter an insulating film of (Si3N4) and pattern the aluminum wiring using photoresist.
O2) film or (SisN4) film,
The aluminum film is etched using an insulating film such as a (Si02) film or a (Si3N4) film, which has good adhesion to the aluminum film, as a mask.

〔作用〕[Effect]

この発明は上記の工程により、サイドエッチ量を最小限
に押さえたアルミニューム配線の形成が達成できる。
According to the present invention, aluminum wiring can be formed with the amount of side etching kept to a minimum through the above-described steps.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例による工程を図について説明
する。なお、第1図において、第2図および第5図と同
一部分にはこれと同一の符号を付し、その再説明は省略
する。第1図(a)〜(d) において、(8)はスパ
ッタアルミニュームII (6)上にスパッタされた酸
化膜(SiOz)または窒化膜(Si3N4)の絶縁膜
である。
Hereinafter, steps according to an embodiment of the present invention will be explained with reference to the drawings. Note that in FIG. 1, the same parts as in FIGS. 2 and 5 are given the same reference numerals, and their redescription will be omitted. In FIGS. 1(a) to 1(d), (8) is an insulating film of oxide film (SiOz) or nitride film (Si3N4) sputtered on sputtered aluminum II (6).

次K、この発明の一実施例によるアルミニューム配線の
形成方法について説明1゛る。ます、第1図(a) K
示すようにコンタクト孔(4)の開孔後、ウェハ全面に
アルミニューム8k <6)ヲスバッタシ、続いて(S
in2)膜または(Si3N4)膜の絶縁膜(3)を約
1.000λの厚さでスパッタする。次ぎにΦ)図のよ
うにアルミニューム配線のバターニングをホトレジスト
(7)で行う。ついで、このホトレジスト(7)をマス
クにして、前記(Sin2)膜または(Si3Nn)膜
の絶fi ! (8)を7レオン系ガスにてエツチング
する(0図参照)。次にアルミニューム膜(6)をりん
酸、または塩素系ガスにてエツチングする。最後にホト
レジスト(7)を除去してアルミニューム配線(6)の
形成が完了する(d図参照)。
Next, a method for forming aluminum wiring according to an embodiment of the present invention will be explained. Figure 1 (a) K
As shown, after forming the contact hole (4), aluminum 8k <6) was applied to the entire surface of the wafer, followed by (S).
An insulating film (3) of in2) film or (Si3N4) film is sputtered to a thickness of about 1.000λ. Next, the aluminum wiring is patterned using photoresist (7) as shown in the figure Φ). Then, using this photoresist (7) as a mask, the (Sin2) film or (Si3Nn) film is removed. (8) is etched with 7 Leon gas (see Figure 0). Next, the aluminum film (6) is etched with phosphoric acid or chlorine gas. Finally, the photoresist (7) is removed to complete the formation of the aluminum wiring (6) (see figure d).

なお、上記実施例では、単一層のアルミニューム配線に
ついて説明したが、これを二層のアルミニューム配線に
ついても上記実施例と同様の効果を奏する。
In the above embodiment, a single layer of aluminum wiring has been described, but the same effects as in the above embodiment can be obtained even when using a double layer of aluminum wiring.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明は、アルミニュームと、より密
着性の良い(Sing)膜または(Si3N4)  膜
をマスクにしてアルミニューム膜のエツチングを行うの
で、レジストパターンからの寸法シフトの少ないアルミ
ニューム配線が得られる効果がある。
As described above, in this invention, since the aluminum film is etched using a (Sing) film or (Si3N4) film with better adhesion to aluminum as a mask, the aluminum film can be etched with less dimensional shift from the resist pattern. This has the effect of providing wiring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)はこの発明の一実施例によるアル
ミニューム配線の形成工程を示した断面図、第2図(a
)〜(C)はアルミニューム配線をウェットエツチング
する場合の従来の工程図、第3図(a)〜(C)は同じ
くアルミニューム配線をドライエツチングする従来の工
程図であるう 図中、(1)はエピタキシャル層、(2)はベース拡散
層、(3)はエミッタ拡散層、(4)はコンタクト孔、
(5)は酸化膜、(6)はアルミニューム膜、(7)は
ホトレジスト、(8)は5i02膜またはS!3Na1
91の絶R膜である。 なお、各図中同一符号は同一または相当部分を示す。 代理人 弁理士 佐 藤 正 年 第1図 一一一\−−1 一一一\−−I 5Cピ丸イと1月美 第2因 $1
1(a) to 1(d) are cross-sectional views showing the process of forming aluminum wiring according to an embodiment of the present invention, and FIG. 2(a)
) to (C) are conventional process diagrams for wet etching aluminum wiring, and Figures 3(a) to (C) are conventional process diagrams for dry etching aluminum wiring. 1) is an epitaxial layer, (2) is a base diffusion layer, (3) is an emitter diffusion layer, (4) is a contact hole,
(5) is an oxide film, (6) is an aluminum film, (7) is a photoresist, and (8) is a 5i02 film or S! 3Na1
91 absolute R film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Patent Attorney Tadashi Sato Figure 1 111\--1 111\--I 5C Pimarui and January Beauty 2nd Cause $1

Claims (1)

【特許請求の範囲】[Claims] (1)ウェハ上にアルミニューム配線を形成する方法に
おいて、スパッタアルミニューム膜上に該アルミニュー
ムと密着性の良い(SiO_2)または(Si_3N_
4)等の絶縁膜をスパッタし、次にこの絶縁膜の上にホ
トレジストで前記アルミニューム配線のパターニングを
行い、次に前記ホトレジストをマスクにして前記スパッ
タアルミニューム膜および絶縁膜をエッチングすること
を特徴とする半導体装置の製造方法。
(1) In the method of forming aluminum wiring on a wafer, a sputtered aluminum film is coated with (SiO_2) or (Si_3N_), which has good adhesion to the aluminum.
4) sputtering an insulating film, then patterning the aluminum wiring on this insulating film with photoresist, and then etching the sputtered aluminum film and the insulating film using the photoresist as a mask. A method for manufacturing a featured semiconductor device.
JP17187985A 1985-08-06 1985-08-06 Manufacture of semiconductor device Pending JPS6232609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17187985A JPS6232609A (en) 1985-08-06 1985-08-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17187985A JPS6232609A (en) 1985-08-06 1985-08-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6232609A true JPS6232609A (en) 1987-02-12

Family

ID=15931485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17187985A Pending JPS6232609A (en) 1985-08-06 1985-08-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6232609A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854134A (en) * 1997-05-05 1998-12-29 Taiwan Semiconductor Manufacturing Company Ltd. Passivation layer for a metal film to prevent metal corrosion
US6528411B2 (en) * 1997-02-27 2003-03-04 Nec Corporation Semiconductor device and method of its fabrication
JP2010129684A (en) * 2008-11-26 2010-06-10 Canon Inc Method of manufacturing semiconductor device, and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528411B2 (en) * 1997-02-27 2003-03-04 Nec Corporation Semiconductor device and method of its fabrication
US5854134A (en) * 1997-05-05 1998-12-29 Taiwan Semiconductor Manufacturing Company Ltd. Passivation layer for a metal film to prevent metal corrosion
JP2010129684A (en) * 2008-11-26 2010-06-10 Canon Inc Method of manufacturing semiconductor device, and semiconductor device

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