JPS62144339A - Inspection method of semiconductor device - Google Patents

Inspection method of semiconductor device

Info

Publication number
JPS62144339A
JPS62144339A JP60286125A JP28612585A JPS62144339A JP S62144339 A JPS62144339 A JP S62144339A JP 60286125 A JP60286125 A JP 60286125A JP 28612585 A JP28612585 A JP 28612585A JP S62144339 A JPS62144339 A JP S62144339A
Authority
JP
Japan
Prior art keywords
voltage
semiconductor device
magnetic field
light emission
inspected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60286125A
Other languages
Japanese (ja)
Other versions
JPH0727949B2 (en
Inventor
Satoshi Suizu
水頭 智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60286125A priority Critical patent/JPH0727949B2/en
Publication of JPS62144339A publication Critical patent/JPS62144339A/en
Publication of JPH0727949B2 publication Critical patent/JPH0727949B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To detect the cause of defective withstanding voltage easily without destroying a semiconductor device to be inspected by applying a magnetic field to the semiconductor device to be inspected together with voltage and measuring the light emission of the semiconductor device to be inspected. CONSTITUTION:Light emission at positions where withstanding voltage is low is increased by a magnetic field by the defect of a semiconductor element. Consequently, the characteristic of said positions can be inspected by low voltage. In a protective-film detective section 8, 15V applied voltage is required in order to observe light emission when a magnetic field is not applied, but light emission is observed by 7V applied voltage when the magnetic field is applied.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の検査方法に係り、特に半導体装置
の耐圧不良をfL極極光光よって調べる検査方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for testing semiconductor devices, and more particularly to a method for testing semiconductor devices for breakdown voltage defects using fL polar light.

従来の技術 従来、例えばGaAs  FETの耐圧測定には、カー
ブトレーサを用い、その電圧電流特性をディスプレイ上
に映し、特定の電流値での電圧値を読みとる方法や、定
電流電源を用い、ゲート接合の逆方向に特定の電流を流
した時の接合間室位差を電圧計を用いて測定する方法等
が一般的に知られている。
Conventional technology Conventionally, for example, to measure the withstand voltage of a GaAs FET, there are methods that use a curve tracer to project the voltage-current characteristics on a display and read the voltage value at a specific current value, and methods that use a constant current power source to measure the gate junction. A commonly known method is to use a voltmeter to measure the potential difference between junctions when a specific current is passed in the opposite direction.

また、被検査半導体装置にそれが作動する以上の電圧を
与えたときに、接合部分から、いわゆる電界発光が見ら
れ、その発光量及び発光箇所を測定することで耐圧不良
箇所を見出すこともできる。
In addition, when a voltage higher than the voltage at which the semiconductor device under test operates is applied, so-called electroluminescence is seen from the junction, and by measuring the amount of light emission and the location of the light emission, it is also possible to find locations with breakdown voltage defects. .

発明が解決しようとする問題点 このような従来の電圧−電流特性によって半導体装置全
体の耐圧として測定している方□法では、耐圧不良箇所
の特定は不可能であった。
Problems to be Solved by the Invention With the conventional method of measuring the breakdown voltage of the entire semiconductor device using voltage-current characteristics, it has been impossible to identify locations with breakdown voltage defects.

また、電界発光による検査方法では被検査半導体装置の
発光量を増加させるために大きな電圧を印加することで
破壊させてしまうという危検注か大きかった。
Furthermore, in the testing method using electroluminescence, a high voltage is applied to increase the amount of light emitted by the semiconductor device to be tested, which poses a risk of destruction.

本発明は、上述の従来例の問題点を解決した半導体装置
の検査方法を提供することを目的としている。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device testing method that solves the problems of the conventional method described above.

問題点を解決するだめの手段 本発明は上記問題点を解決するため、被検査半導体装置
に電圧と共に磁場を加え、被検査半導体装置の発光を測
定する半導体装置の検査方法である。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is a method of testing a semiconductor device in which a voltage and a magnetic field are applied to the semiconductor device to be tested and the light emission of the semiconductor device to be tested is measured.

作  用 本発明の方法により、半導体素子の欠陥によって耐圧が
低い箇所の発光が磁界によって増強される。したがって
、同箇所の特定を低い電圧で検査することが可能である
Effect: According to the method of the present invention, light emission at a location where the breakdown voltage is low due to a defect in a semiconductor element is enhanced by a magnetic field. Therefore, it is possible to inspect the same location using a low voltage.

実施例 第1図はGaAs  FETの素子平面図と、発光量を
増加させる為の磁場の向さを示している。図中、1はゲ
ート、2はソース、3はドレイン、4は活性層領域、5
はゲートフィンガーである。図に示す磁界了の磁場を加
えた時には、たとえば、FETのゲート1に12■の逆
方向電圧を印加すればゲートフィンガー5とドレイン3
との間のゲート発光領域らで発光が見られるが、磁場を
加えないときには、同じ発光を観測するために26Vの
電圧が必要であった。
Embodiment FIG. 1 shows a plan view of a GaAs FET and the direction of a magnetic field to increase the amount of light emitted. In the figure, 1 is a gate, 2 is a source, 3 is a drain, 4 is an active layer region, and 5
is the gate finger. When a magnetic field of the magnitude shown in the figure is applied, for example, if a reverse voltage of 12 cm is applied to the gate 1 of the FET, the gate finger 5 and the drain 3
Light emission can be seen in the gate light emitting region between the two, but when no magnetic field is applied, a voltage of 26 V is required to observe the same light emission.

第2図はマスクずれによる発光ノくターンを示す平面図
であり、第1図と同一の構成には同一の番号を付してい
る。磁場を加えないとき、発光を観測するには20Vの
印加電圧が必要であったが、第1図の場1合と同様の磁
場を加えると、8vを印加すれば発光が観測された。
FIG. 2 is a plan view showing a light emitting turn caused by mask displacement, and the same components as in FIG. 1 are given the same numbers. When no magnetic field was applied, an applied voltage of 20 V was required to observe luminescence, but when a magnetic field similar to that in case 1 of FIG. 1 was applied, luminescence was observed when 8 V was applied.

第3図は、保護膜欠陥部8での発光パターンを示す平面
図であり、第1図と同一の構成には同一の着号を付して
いる。同図中8は保護膜欠陥を表わしている。磁場を加
えないとき、発光を観測するには16vの印加電圧が必
要であったが、第1図の場合と同様の磁場を加えると、
7■で発光が観測された。
FIG. 3 is a plan view showing a light emission pattern at the protective film defective portion 8, and the same components as in FIG. 1 are given the same numbers. 8 in the figure represents a protective film defect. When no magnetic field was applied, an applied voltage of 16 V was required to observe luminescence, but when a magnetic field similar to that in Figure 1 was applied,
Luminescence was observed at 7■.

また、第4図にGaAs  FETの高温動作試験(チ
ャネル温度250℃)1000時間後において、ゲート
の耐圧が10%低下した試料の発光パターンを示す平面
図であり、第1図と同一の構成には同一の番号を付、し
ている。従来では発光を観測するために20Vの電圧を
必要としだが、第1図と同様の磁場を加えると、印加電
圧10Vで発光を観測できた。試験前の状態では、第1
図と同様の磁場と電圧を12Vを印加することで第1図
のようにゲート全体からの発光が見られていた。
In addition, Fig. 4 is a plan view showing the light emission pattern of a sample in which the gate breakdown voltage decreased by 10% after 1000 hours of a high temperature operation test (channel temperature 250°C) of a GaAs FET, and it has the same configuration as Fig. 1. have the same number. Conventionally, a voltage of 20V was required to observe luminescence, but when a magnetic field similar to that shown in Fig. 1 was applied, luminescence could be observed with an applied voltage of 10V. In the state before the test, the first
By applying the same magnetic field and voltage of 12V as shown in the figure, light emission from the entire gate was observed as shown in Figure 1.

そして、更に試験を継続することにより、1000時間
の時点で発光が見られたゲー)Id所で断線し、FET
が正常に動作しなくなった。
Then, by continuing the test, the wire broke at the point where light emission was observed at 1000 hours, and the FET
is no longer working properly.

このようにして、ゲート断線による故障を発光箇所を調
べて予測できたが、従来の磁場を加えない方法によると
、20ケ中7ケを焼損させ破壊したが、本実施例によれ
ば40ケ全て破壊させずに検査することができた。
In this way, it was possible to predict failures due to gate disconnections by examining the light emitting locations, but with the conventional method that did not apply a magnetic field, 7 out of 20 gates were burnt out and destroyed, but according to this example, 40 gates were destroyed. I was able to inspect everything without destroying it.

以上ばGaAs  FETの事例について述べてきたも
のであるが、81半導体装置の場合も、作動する電圧を
こえる高い電圧を印加することにより発光を起こすこと
から、本発明が81半導体装置に適用できるのは言うま
でもない。
The above has described the case of GaAs FET, but the present invention can also be applied to the 81 semiconductor device because light emission occurs when a high voltage exceeding the operating voltage is applied to the 81 semiconductor device. Needless to say.

発明の効果 以上の説明で明らかなように、本発明によれば、耐圧不
良原因を、被検査半導体装置を破壊させることなく、容
易に検出でき、実用上きわめて有効である。
Effects of the Invention As is clear from the above description, according to the present invention, the cause of breakdown voltage failure can be easily detected without destroying the semiconductor device under test, and is extremely effective in practice.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はGaAs  FET素子と磁場の向き及び発光
パターンを示す模式図、第2図はマスクずれによる発光
パターンを示す模式図、第3図は保護膜欠陥部での発光
パターンを示す模式図、第4図はGaAs  F E 
Tの高温動作試験で耐圧が減少した試料の発光パターン
を示す模式図である。 1・・・・・・ゲート、2・・・・・・ソース、3・・
・・・・ドレイン、4・・・・・・活性層領域、5・・
・・・・ゲートフィンガー、6・・・・・・ゲート発光
領域、7・・・・・・磁界、8・・・・・・保護膜欠陥
部。
FIG. 1 is a schematic diagram showing the GaAs FET element, the direction of the magnetic field, and the light emission pattern, FIG. 2 is a schematic diagram showing the light emission pattern due to mask misalignment, and FIG. 3 is a schematic diagram showing the light emission pattern at the defective part of the protective film. Figure 4 shows GaAs F E
FIG. 3 is a schematic diagram showing a light emission pattern of a sample whose breakdown voltage has decreased in a high temperature operation test of T. 1...Gate, 2...Source, 3...
...Drain, 4...Active layer region, 5...
. . . Gate finger, 6 . . . Gate light emitting region, 7 . . . Magnetic field, 8 . . . Protection film defect.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の耐圧不良を検査するに際し、半導体装置に
対して、電界と同時に磁場を加えて検査することを特徴
とする半導体装置の検査方法。
1. A method for testing a semiconductor device, characterized in that when testing a semiconductor device for breakdown voltage defects, the semiconductor device is tested by applying an electric field and a magnetic field at the same time.
JP60286125A 1985-12-19 1985-12-19 Semiconductor device inspection method Expired - Lifetime JPH0727949B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60286125A JPH0727949B2 (en) 1985-12-19 1985-12-19 Semiconductor device inspection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60286125A JPH0727949B2 (en) 1985-12-19 1985-12-19 Semiconductor device inspection method

Publications (2)

Publication Number Publication Date
JPS62144339A true JPS62144339A (en) 1987-06-27
JPH0727949B2 JPH0727949B2 (en) 1995-03-29

Family

ID=17700251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60286125A Expired - Lifetime JPH0727949B2 (en) 1985-12-19 1985-12-19 Semiconductor device inspection method

Country Status (1)

Country Link
JP (1) JPH0727949B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014153314A (en) * 2013-02-13 2014-08-25 Dainippon Screen Mfg Co Ltd Inspection equipment and inspection method
CN106526445A (en) * 2016-11-25 2017-03-22 成都海威华芯科技有限公司 Method for fast measuring thermal steady-state characteristic of GaN HEMT

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS576371A (en) * 1980-06-12 1982-01-13 Toshiba Corp Dielectric strength test method
JPS5946868A (en) * 1982-09-10 1984-03-16 Hitachi Ltd Non-destructive inspection of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS576371A (en) * 1980-06-12 1982-01-13 Toshiba Corp Dielectric strength test method
JPS5946868A (en) * 1982-09-10 1984-03-16 Hitachi Ltd Non-destructive inspection of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014153314A (en) * 2013-02-13 2014-08-25 Dainippon Screen Mfg Co Ltd Inspection equipment and inspection method
CN106526445A (en) * 2016-11-25 2017-03-22 成都海威华芯科技有限公司 Method for fast measuring thermal steady-state characteristic of GaN HEMT
CN106526445B (en) * 2016-11-25 2019-02-01 成都海威华芯科技有限公司 A kind of method for fast measuring of the hot steady-state characteristic of GaN HEMT

Also Published As

Publication number Publication date
JPH0727949B2 (en) 1995-03-29

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