WO2022075804A1

WO2022075804A1 - Method for inspecting semiconductor device having function of determining trap site information, and device for inspecting semiconductor device

Info

Publication number: WO2022075804A1
Application number: PCT/KR2021/013885
Authority: WO
Inventors: 김규태; 이국진; 남상진; 박현익; 김연수; 이재우; 김도윤
Original assignee: 고려대학교 산학협력단
Priority date: 2020-10-08
Filing date: 2021-10-08
Publication date: 2022-04-14
Also published as: KR102442512B1; KR20220047068A

Abstract

A method for inspecting a semiconductor device is provided. The method for inspecting a semiconductor device may comprise the steps of: preparing a semiconductor device under test; measuring a current signal outputted from the semiconductor device under test; amplifying the current signal; calculating an amount of change in the current value over time from the amplified current signal; converting the amount of change in the current value with time into a probability density function with respect to the amount of change in the current value; and extracting information on a trap site of the semiconductor device under test from the probability density function.

Description

A semiconductor device inspection method and semiconductor device inspection device having a function of determining trap site information

The present application relates to a semiconductor device inspection method and a semiconductor device inspection device, and more particularly, to a semiconductor device inspection method and semiconductor device inspection apparatus having a function of determining trap site information of a semiconductor device.

Semiconductor inspection equipment can be broadly classified into main tester, probe station, handler, and burn-in equipment. , It is classified into component inspection equipment such as handlers that evaluates the normal operation of the package at the final stage after completing the semiconductor process, and module inspection equipment that inspects whether the module works properly in the state of a module with several semiconductor elements installed on the PCB. can do.

With the development of the semiconductor industry, the technical demand for semiconductor inspection equipment and semiconductor inspection methods is gradually increasing.

For example, in Korean Patent Laid-Open Publication No. 10-2018-0129057, a sample wafer is inspected to detect a defect on the sample wafer, attribute information of the defect on the sample wafer, and the an inspector that generates information about a location where a defect has occurred, and selects a layout pattern on a sample layout design corresponding to the location information; an electron microscope for taking an enlarged image of the sample wafer based on the location information where the defect has occurred on the sample wafer; and by machine learning, attribute information of the defect on the sample wafer and the pre-risk predicted by the predetermined layout pattern as input variables, and output the risk of the defect determined from the enlarged image of the sample wafer Disclosed is a semiconductor device inspection system including a modeling module for generating a defect model using force parameters.

One technical problem to be solved by the present application is to provide a highly reliable semiconductor device inspection method and semiconductor device inspection apparatus.

Another technical problem to be solved by the present application is to provide a high-speed semiconductor device inspection method and a semiconductor device inspection apparatus.

Another technical problem to be solved by the present application is to provide an inexpensive semiconductor device inspection method and semiconductor device inspection apparatus.

Another technical problem to be solved by the present application is to provide a semiconductor device inspection method and a semiconductor device inspection apparatus having a high inspection speed.

Another technical problem to be solved by the present application is to provide a method for inspecting a semiconductor device capable of determining trap site information, and an apparatus for inspecting a semiconductor device.

Another technical problem to be solved by the present application is to provide a method for inspecting a semiconductor device for a memory or display, and an apparatus for inspecting a semiconductor device.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above technical problem, the present application provides a method of inspecting a semiconductor device.

According to an embodiment, the method of inspecting the semiconductor device includes preparing a semiconductor device under test, measuring a current signal output from the semiconductor device under test, amplifying the current signal, and the amplified current calculating a change amount of the current value with time from a signal, converting the change amount of the current value with time into a probability density function with respect to the change amount of the current value, and from the probability density function, the semiconductor device under test It may include the step of extracting information about the trap site.

According to an embodiment, the information on the trap site may include a type of trap site of the semiconductor device under test, a position of the trap site, a density of the trap site, and a distribution of the trap site.

According to an embodiment, the extracting of the information on the trap site of the semiconductor device under test from the probability density function may include: The method may include preparing unique reference probability density functions and extracting information on a trap site of the semiconductor device under test by using the reference probability density functions.

According to an embodiment, the extracting of the information on the trap site of the semiconductor device under test from the probability density function may include first to n-th ones matching the probability density function among the reference probability density functions. (n is a natural number equal to or greater than 2) selecting a reference probability density function, and types of trap sites, positions of trap sites, densities of trap sites, and trap sites corresponding to the first to n-th reference probability density functions It may include extracting the distribution of.

According to an embodiment, the semiconductor device under test may include a memory semiconductor device.

According to an embodiment, the current signal may include a drain current value of the memory semiconductor device.

In order to solve the above technical problem, the present application provides an apparatus for inspecting a semiconductor device.

According to an embodiment, the apparatus for inspecting the semiconductor device includes a current signal measuring unit for measuring a current signal from the semiconductor device under test, an amplifying unit for amplifying the current signal, and a current value from the amplified current signal over time. A current value change amount calculator for calculating a change amount, a probability density function converter for converting the change amount of the current value with time into a probability density function with respect to the change amount of the current value, and from the probability density function, It may include a trap site information check unit for extracting information on the trap site.

According to an embodiment, the trap site information check unit includes a data storage unit for storing unique reference probability density functions according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site; and a matching unit that extracts information on trap sites of the semiconductor device under test by using the reference probability density functions.

According to an embodiment, the matching unit selects a first to nth (n is a natural number equal to or greater than 2) reference probability density function that matches the probability density function from among the reference probability density functions, It may include extracting the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site corresponding to the 1 to nth reference probability density function.

According to an embodiment, the apparatus for inspecting the semiconductor device may include a plurality of reference probability density functions and a storage unit configured to store trap information corresponding to the plurality of reference probability density functions.

According to an embodiment, the trap information may include a type of trap site, a position of the trap site, a density of the trap site, and a distribution of the trap site.

According to an embodiment of the present application, after measuring the current signal output from the semiconductor device under test, amplifying the current signal, calculating the amount of change in the current value with time, and calculating the amount of change in the current value with time, the current A probability density function with respect to a change amount of a value may be converted, and information on a trap site of the semiconductor device under test may be extracted from the probability density function. That is, information on the trap site of the semiconductor device under test can be extracted by a simple method of applying a test current to the semiconductor device under test and analyzing the current signal output from the semiconductor device under test.

Accordingly, information on the trap site of the semiconductor device under test can be easily analyzed without measuring the charge pumping capacitance of the semiconductor device under test. A method of inspecting a semiconductor device with high reliability may be provided.

1 is a view for explaining a trap site of a semiconductor device under test according to an embodiment of the present application.

2 is a graph for explaining an amount of change in a Vth value of a semiconductor device under test according to an embodiment of the present application.

3 is a diagram illustrating an energy van diagram of a semiconductor under test according to an embodiment of the present application.

4 is a view for explaining modeling of trap density of a semiconductor under test according to an embodiment of the present application.

5 is a flowchart illustrating a method of inspecting a semiconductor device under test according to an exemplary embodiment of the present application.

6 is a diagram illustrating a probability density function of a semiconductor device under test in a method for inspecting a semiconductor device under test according to an embodiment of the present application.

7 is a diagram illustrating probability density functions for reference in a method of inspecting a semiconductor device under test according to an embodiment of the present application.

8 is a diagram illustrating matching a probability density function for reference to a probability density function of a semiconductor device under test in a method for testing a semiconductor device under test according to an embodiment of the present application.

9 is a block diagram illustrating an apparatus for inspecting a semiconductor device under test according to an exemplary embodiment of the present application.

10 is a block diagram illustrating a trap site information check unit included in an apparatus for inspecting a semiconductor device under test according to an embodiment of the present application.

11 is a graph illustrating a change amount of a current value according to time of a semiconductor device according to an experimental example of the present application.

12 is a graph of measuring trap and detrap times according to a gate voltage of a semiconductor device according to an experimental example of the present application.

13 is a graph in which a normalized current value change amount according to time of a semiconductor device according to an experimental example of the present application is measured.

14 and 15 illustrate a probability density function of a semiconductor device according to an experimental example of the present application.

16 is a Gaussian mixture model used for analyzing a probability density function of a semiconductor device according to an experimental example of the present application.

17 is a result of analyzing trap site information of a semiconductor device according to an experimental example of the present application.

18 is a view for explaining a power spectrum density, the number of traps per volume, and a scattering parameter of a semiconductor device according to an embodiment of the present application.

19 is a view for explaining a trap configuration of a semiconductor device according to an experimental example of the present application.

20 is a time-lag graph of a semiconductor device under test according to an experimental example of the present application.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In this specification, when a component is referred to as being on another component, it means that it may be directly formed on the other component or a third component may be interposed therebetween. In addition, in the drawings, thicknesses of films and regions are exaggerated for effective description of technical content.

In addition, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In addition, in this specification, 'and/or' is used in the sense of including at least one of the components listed before and after.

In the specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to designate that a feature, number, step, element, or a combination thereof described in the specification exists, but one or more other features, number, step, configuration It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in the following description of the present invention, if it is determined that a detailed description of a related well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a diagram for explaining a trap site of a semiconductor device under test according to an embodiment of the present application, and FIG. 2 is a graph for explaining an amount of change in Vth value of a semiconductor device under test according to an embodiment of the present application; 3 is a diagram illustrating an energy van diagram of a semiconductor under test according to an embodiment of the present application, and FIG. 4 is a view for explaining modeling of a trap density of a semiconductor under test according to an embodiment of the present application.

1 and 2, even in the case of semiconductor devices (ref, 1, 2) manufactured with the same configuration and the same material, the degree of deterioration of the semiconductor device varies depending on the manufacturing process conditions and driving environment of the semiconductor device, As shown in FIG. 1 , the energy level and trap density at which traps and defects are formed may be formed differently.

For this reason, as shown in FIG. 2 , the amount of change in the Vth value may be different under deterioration conditions such as NBTI, PBTI, and hot carrier injection.

3 and 4, an energy van diagram, trap site distribution, and modeling are shown for a semiconductor device having a SiGe/Si/SiO2/HfO2/TiN structure. ) and (c) are for a semiconductor device having a relatively long channel, and FIGS. 3 (b), 4 (b) and (d) are for a semiconductor device having a relatively short channel. In (a) and (b) of FIG. 4, t _relax is a time at which carriers are emitted, and may include information on the energy level and location of the trap site, and in (c) and (d) of FIG. 4 , ττ is It means the time during which the carrier is trapped or detrapped, and may include information on the energy level and location of the trap site.

As can be seen from FIG. 3 , not only the energy position of the trap site, but also the physical positions of the carrier (hole or electron) and the trap site. Accordingly, the tunneling length changes. Therefore, the carrier located at the Fermi level and the trap site of the insulating film are mutually As a result, the tendency of carriers to trap and detrap is changed, which may cause a large change in the reliability and deterioration of the semiconductor device. That is, the tendency of carriers to trap and detrap may be changed according to the formation position of the Fermi level according to the doping position of the dopant in the channel region or the thickness of the insulating film.

As shown in (b) and (d) of Figure 4, a semiconductor device having a relatively short channel length has a relatively small number of trap sites with respect to time stress (carrier capturing) or relaxation (carrier emission). , which may result in a step-like characteristic.

On the other hand, as shown in (a) and (c) of FIG. 4 , a semiconductor device having a relatively long channel length exhibits mixed characteristics while a relatively large number of trap sites effectively act, thereby defining and identifying trap sites individually. not easy to do

Accordingly, there is a need for a semiconductor device inspection method and semiconductor device inspection equipment capable of discriminating information on trap sites of the semiconductor device.

5 is a flowchart illustrating a method for inspecting a semiconductor device under test according to an embodiment of the present application, and FIG. 6 is a probability density function of a semiconductor device under test in the method for inspecting a semiconductor device under test according to an embodiment of the present application FIG. 7 is a diagram illustrating probability density functions for reference in the inspection method of a semiconductor device under test according to an embodiment of the present application, and FIG. 8 is a diagram of a semiconductor device under test according to an embodiment of the present application It is a diagram showing the matching of the probability density function for reference to the probability density function of the semiconductor device under test in the inspection method.

5 to 8 , a semiconductor device under test is prepared ( S110 ).

According to an embodiment, the semiconductor device under test may be a memory device. For example, the semiconductor device under test may include various memory devices such as a NAND memory, a DRAM, an SRAM, a magnetic memory (MRAM), and a phase change memory (PRAM). .

Alternatively, according to another embodiment, the semiconductor device under test may include a logic IC, an image sensor, a thin film transistor for a display, and the like.

A test current may be applied to the semiconductor device under test, and a current signal output from the semiconductor device under test may be measured ( S120 ).

According to an embodiment, the current signal may be a drain current value of the memory semiconductor device.

The frequency of the test current and the magnitude of the current value may be controlled according to the type of the semiconductor device under test.

For example, when a current of a sub-threshold region is applied to the semiconductor device under test, a limited carrier concentration may be generated in a channel region of the semiconductor device under test, and accordingly, traps existing in the semiconductor device under test The impact by the site can be identified more clearly.

The current signal output from the semiconductor device under test may be amplified ( S130 ).

The current signal output from the semiconductor device under test may be slightly changed according to the type of trap site, the location of the trap site, the density of the trap site, and the distribution of the trap site of the semiconductor device under test.

As described above, the current signal is amplified, so that minute fluctuations in the current signal can be amplified.

From the amplified current signal, the amount of change in the current value with time may be calculated (S140).

The amount of change in the current value with time may be calculated as a normalized value. For example, calculating the change amount of the current value with time from the amplified current signal may be calculated using a program implemented in a programming language (eg, Python, or PyTorch).

The amount of change in the current value with time may be converted into a probability density function with respect to the amount of change in the current value (S150).

Specifically, for example, as shown in FIG. 6 , it may be converted into a probability density function with respect to the amount of change in the current value. That is, after the current signal output from the semiconductor under test is amplified, it may be converted into the probability density function with respect to the amount of change in the current value.

Information on the trap site of the semiconductor device under test may be extracted from the probability density function (S160).

Depending on the type of trap site present in the semiconductor device under test, the location of the trap site, the density of trap sites, and the distribution of trap sites, a unique probability density function for the amount of change in the current value output from the semiconductor device under test is may exist.

Accordingly, the step of extracting the information on the trap site of the semiconductor device under test from the probability density function includes a unique reference according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site. preparing probability density functions for reference, selecting a first to nth (n is a natural number equal to or greater than 2) reference probability density function matching the probability density function from among the reference probability density functions, and the The method may include extracting the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site corresponding to the first to nth reference probability density functions.

That is, by selecting the first to nth reference probability density functions matching the probability density function, the type of trap site, the location of the trap site, and the trap site corresponding to the first to nth reference probability density functions are selected. The density and distribution of trap sites may be defined as information on trap sites of the semiconductor device under test.

Specifically, for example, the probability density function is configured as shown in FIG. 6 , and the reference probability density functions are as shown in FIG. 7 , F1-1, F1-2, F1-3, F2- 1, F2-2, and F2-3. Among the reference probability density functions F1-1, F1-2, F1-3, F2-1, F2-2, and F2-3 of FIG. 7, the probability density value according to the change amount of the current value is Compared with the probability density function of 6, the first reference probability density function F1-1 and the second reference probability density function F2-2 that are substantially identical or closest are as shown in FIG. Likewise, it can be selected. In this case, the type of trap site, the location of the trap site, the density of the trap site, and the trap corresponding to the first reference probability density function F1-1 and the second reference probability density function F2-2 The distribution of sites may be defined as information on trap sites of the semiconductor under test.

In addition, according to an embodiment, the step of selecting the first to n-th reference probability density functions matching the probability density function from among the reference probability density functions may be performed through machine learning and deep learning. can

According to an embodiment of the present application, after measuring the current signal output from the semiconductor device under test, amplifying the current signal, calculating the amount of change in the current value with time, The probability density function for the change amount of the current value may be converted from the change amount, and information on the trap site of the semiconductor device under test may be extracted from the probability density function using the reference probability density functions. That is, information on the trap site of the semiconductor device under test can be extracted by a simple method of applying the test current to the semiconductor device under test.

Accordingly, information on the trap site of the semiconductor device under test can be easily analyzed without measuring the charge pumping capacitance of the semiconductor device under test. A method of testing may be provided.

Hereinafter, an example of an apparatus for testing a semiconductor device under test for implementing the method for testing a semiconductor device under test according to an embodiment of the present application described above will be described with reference to FIGS. 9 and 10 .

9 is a block diagram illustrating an apparatus for inspecting a semiconductor device under test according to an embodiment of the present application, and FIG. 10 is a trap site information confirmation unit included in the inspection apparatus for a semiconductor element under test according to an embodiment of the present application. It is a block diagram for explanation.

9 and 10 , an apparatus for inspecting a semiconductor device under test according to an embodiment of the present invention includes a current signal measuring unit 110 , an amplifying unit 120 , a current value change calculating unit 130 , and a probability density. It may include a function conversion unit 140 and a trap site information check unit 150 .

The current signal measuring unit 110 may measure a current signal from the semiconductor device under test to which the test current is applied, and the amplifying unit 120 may amplify the current signal.

The current value change calculation unit 130 may calculate a change amount of the current value with time from the amplified current, and the probability density function converter 140 converts the change amount of the current value with time to the change amount of the current value. It can be transformed into a probability density function according to

The trap site information check unit 150 may include a data storage unit 152 and a matching unit 154 .

The data storage unit 152 may store unique reference probability density functions according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site.

The matching unit 154 may extract information on the trap site of the semiconductor device under test by using the reference probability density functions. Specifically, the matching unit 154 selects first to nth (n is a natural number equal to or greater than 2) reference probability density function matching the probability density function from among the reference probability density functions, The type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site corresponding to the first to nth reference probability density functions may be extracted.

It will be understood by those skilled in the art that the above-described embodiments of the present invention may be performed by computer program instructions. These computer program instructions may be embodied in a processor of a general purpose computer, special purpose computer, or other programmable data processing equipment, such that the instructions performed by the processor of the computer or other programmable data processing equipment are not shown in the flowchart block(s). It creates means for performing the functions of the embodiments of the invention.

These computer program instructions may also be stored in a computer-usable or computer-readable memory that may direct a computer or other programmable data processing equipment to implement a function in a particular manner, and thus the computer-usable or computer-readable memory. The instructions stored in the . It is also possible to produce a manufactured item including an instruction means for performing a function according to an embodiment of the present invention.

The computer program instructions may also be mounted on a computer or other programmable data processing equipment, such that a series of operational steps are performed on the computer or other programmable data processing equipment to create a computer-executed process to create a computer or other programmable data processing equipment. It is also possible that instructions for performing the processing equipment provide steps for performing the functions described in the flowchart block(s).

Additionally, each block may represent a module, segment, or portion of code that includes one or more executable instructions for executing specified logical function(s). It is also possible for the functions mentioned in blocks to occur out of order in some alternative implementations. For example, two blocks shown one after another may be performed substantially simultaneously, or the blocks may sometimes be performed in the reverse order according to a corresponding function.

Hereinafter, specific experimental examples according to the above-described embodiments of the present application will be described.

Preparation of semiconductor devices according to experimental examples

A silicon gate all around type transistor was prepared. Specifically, a gate all-around type transistor formed of polysilicon was prepared. Thereafter, a DC voltage in the sub-threshold region is applied to the transistor, amplifying the fine tremor of the output current, normalizing the amount of change in the current value with time from the amplified current signal, and the amount of change in the current value with time is the current It was converted into a probability density function according to the amount of change in the value, and information about the trap site of the transistor was confirmed.

Referring to FIG. 11 , as described above, the amount of change in the current value with time for the transistor according to the experimental example was normalized.

In FIG. 11 , τ _l denotes a time at which carriers are trapped, and τ _h denotes a time at which carriers are detrapped. Carriers present at the Fermi level may be trapped or de-trapped at the trap site, and it can be seen that the amount of change in the current value increases or decreases according to the trap or de-trap of the carriers.

In addition, it can be seen that the variation in the amount of change in the current value is different according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site.

12, a transistor according to the above-described experimental example is prepared, a transistor having a channel length of 900 nm and a channel width of 85 nm is prepared, a transistor having a channel length of 900 nm and a channel width of 165 nm is prepared, , and the time during which carriers were trapped and detrapped according to the gate voltage was measured.

As can be seen from FIG. 12 , it can be seen that the time for carriers to be trapped and detrapped is longer in the case of the transistor having the narrow channel width compared to the transistor having the wide channel width. That is, it can be seen that the time during which carriers are trapped and detrapped varies according to the structure, dimensions, and characteristics of the transistor.

Referring to FIG. 13 , the amount of change in the current value with time for the transistor according to the above-described experimental example was normalized. As can be seen from FIG. 13 , it can be confirmed that the current value fluctuates with time.

14 and 15 , FIG. 14 is a probability density function of a transistor having a channel length of 900 nm and a channel width of 85 nm described with reference to FIG. 12 , and FIG. 14 (a) is before Vth is applied. 14B shows after Vth is applied. 15 is a probability density function of a transistor having a channel length of 900 nm and a channel width of 165 nm, which has been described with reference to FIG. 12 . FIG. 15 (a) is before Vth is applied, and FIG. 15 (b) is Vth applied. it is after

As can be seen from FIGS. 14 and 15 , it can be confirmed that the probability density function with respect to the amount of change in the current value is changed according to the structure, dimensions, and characteristics of the transistor, and the probability density function is changed according to whether Vth is applied. can check that That is, it can be seen that the probability density function changes according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site.

16 is a Gaussian mixture model used for analyzing a probability density function of a semiconductor device according to an experimental example of the present application, and FIG. 17 is a result of analyzing trap site information of a semiconductor device according to an experimental example of the present application.

16 and 17 , the probability density functions shown in FIGS. 14 and 15 may be matched by a combination of a plurality of reference probability density functions.

It may be performed through machine learning and deep learning using a Gaussian mixture model shown in FIG. 16 . Specifically, as described above, a unique probability density function may exist according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site, and the intrinsic probability density function has a unique average It can have a value (u) and a value of covariance (σ). By selecting and combining unique probability density functions by machine learning and deep learning using a Gaussian mixture model, the probability density function shown in FIGS. 14 and 15 is implemented, and the type of trap site possessed by the selected unique probability density functions , the position of the trap site, the density of the trap site, and the distribution of the trap site may be defined as trap site information of the transistor according to the experimental example.

Referring to FIG. 17, (a) of FIG. 17 is a graph showing the number of traps per volume as an analysis result of a probability density function of a transistor according to an experimental example through a Gaussian mixture model, and (b) of FIG. 17 is a Gaussian mixture model It is a graph showing a scattering parameter as an analysis result of a probability density function of a transistor according to an experimental example.

Specifically, the number of traps per volume and scattering parameters were calculated through the power spectral density in the frequency domain calculated through the Fourier transform of the current variation.

18 (a) and (b) are experimental examples of calculated power spectral densities in devices having different structures, and it can be seen that fittings are performed in different shapes depending on the type of trap with respect to the actually flowing current. In fact, referring to FIGS. 18 ( c ) and 18 ( d ) , it was confirmed that the number of traps per volume and scattering parameters were different depending on the structure of the device.

Referring to FIG. 19, (a) of FIG. 19 is a measurement of a current wave of a semiconductor device under test according to a sampling time. Figure 19 (b) is a distribution histogram of Figure 19 (a).

As can be seen from FIGS. 19A and 19B , it can be confirmed that the current wave of the semiconductor under test varies with time, and the current wave depends on the structure, deterioration degree, and trap configuration of the semiconductor device under test. It can be seen that this is different.

Referring to FIG. 20, (a) of FIG. 20 is a time-lag graph of FIG. 19 (a), and FIG. 20 (b) is a frequency domain after Fourier transform for FIG. 20 (a). .

Referring to FIGS. 20A and 20B , in the time-lag graph extracted from the real-time current wave, it is possible to configure a trap for degradation and reliability check by k- means clustering. In addition, it can be seen that the power spectral density expressed in the frequency diagram can also be classified differently.

As mentioned above, although the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to specific embodiments and should be construed according to the appended claims. In addition, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the present invention.

The semiconductor device inspection method and semiconductor device inspection apparatus having a function of determining trap site information according to an embodiment of the present application may be utilized for inspection of various semiconductor devices, such as a memory device, a logic device, and a display semiconductor device.

Claims

preparing a semiconductor device under test;

measuring a current signal output from the semiconductor device under test;

amplifying the current signal;

calculating a change amount of a current value with time from the amplified current signal;

converting the amount of change in the current value with time into a probability density function with respect to the amount of change in the current value; and

and extracting information on trap sites of the semiconductor device under test from the probability density function.
According to claim 1,

The information on the trap site includes a type of trap site of the semiconductor device under test, a position of the trap site, a density of the trap site, and a distribution of the trap site.
According to claim 1,

The step of extracting information on the trap site of the semiconductor device under test from the probability density function,

Probability density functions for reference are prepared according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site,

and extracting information on a trap site of the semiconductor device under test by using the reference probability density functions.
4. The method of claim 3,

The step of extracting information on the trap site of the semiconductor device under test from the probability density function,

selecting a first to nth (n is a natural number equal to or greater than 2) reference probability density function matching the probability density function from among the reference probability density functions; and

and extracting the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site corresponding to the first to nth reference probability density functions.
According to claim 1,

and the semiconductor element under test is a memory semiconductor element.
6. The method of claim 5,

and the current signal is a drain current value of the memory semiconductor device.
a current signal measuring unit measuring a current signal from the semiconductor device under test;

an amplifying unit amplifying the current signal;

a current value change amount calculation unit for calculating a change amount of the current value with time from the amplified current signal;

a probability density function conversion unit converting the amount of change in the current value with time into a probability density function with respect to the amount of change in the current value; and

and a trap site information checker configured to extract information on a trap site of the semiconductor device under test from the probability density function.
8. The method of claim 7,

The trap site information confirmation unit,

a data storage unit for storing unique reference probability density functions according to the type of trap site, the position of the trap site, the density of the trap site, and the distribution of the trap site; and

and a matching unit configured to extract information on a trap site of the semiconductor device under test by using the reference probability density functions.
9. The method of claim 8,

The matching unit selects a first to nth (n is a natural number equal to or greater than 2) reference probability density function that matches the probability density function from among the reference probability density functions, and the first to nth reference An apparatus for inspecting a semiconductor device, comprising extracting a type of trap site, a position of the trap site, a density of the trap site, and a distribution of the trap site corresponding to the probability density function.
A semiconductor device inspection apparatus comprising: a plurality of reference probability density functions; and a storage unit configured to store trap information corresponding to the plurality of reference probability density functions.
11. The method of claim 10,

The trap information includes a type of trap site, a position of the trap site, a density of the trap site, and a distribution of the trap site.