JPS61128541A - Reliability testing method of semiconductor device - Google Patents
Reliability testing method of semiconductor deviceInfo
- Publication number
- JPS61128541A JPS61128541A JP25101384A JP25101384A JPS61128541A JP S61128541 A JPS61128541 A JP S61128541A JP 25101384 A JP25101384 A JP 25101384A JP 25101384 A JP25101384 A JP 25101384A JP S61128541 A JPS61128541 A JP S61128541A
- Authority
- JP
- Japan
- Prior art keywords
- test
- semiconductor device
- semiconductor element
- semiconductor
- testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は複数の半導体素子を直流電源装置に接続した
状態で試験槽に投入して一括して電流を流して試験を行
なう半導体装置の信頼性試験方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] This invention improves the reliability of semiconductor devices in which a plurality of semiconductor devices connected to a DC power supply are placed in a test chamber and tested by passing current all at once. Concerning sex testing methods.
第２図は従来の半導体装置の信頼性試験方法を示す図で
１図において、（１）は試験される半導体素子、（２）
はこの半導体素子（１）複数個を装着したエージング基
板、（３）は直流電圧源、（４）はリード線、（５）は
恒温槽である試験槽である。Figure 2 is a diagram showing a conventional reliability testing method for semiconductor devices. In Figure 1, (1) is the semiconductor element to be tested, (2)
is an aging board on which a plurality of semiconductor elements (1) are mounted, (3) is a DC voltage source, (4) is a lead wire, and (5) is a test chamber which is a thermostatic chamber.
次に、−ｔ″の試４験方法を連続動作寿命試験について
説明する。まず、複数の半導体素子（１）を、すでに所
定のバイアス印加条件で作成されたエージング基板（２
）に装着する。ついで、このエージング基板（２）と直
流電圧源（３）をリード線（４）で結び、所定の一定電
圧を印加した状態で所定温度の恒温槽である試験槽（５
）に投入する。このようにして試験槽（５）の中の所定
の環境状態の許で複数の半導体素子（１）に一括して試
験電流を流し続ける。その後不良の発生の有無を調べる
ために、半導体素子（１）とエージング基板（２）とを
試験槽（５）より取出し、常温の中で放置し冷却する。Next, we will explain the continuous operation life test method for -t'' test. First, a plurality of semiconductor devices (1) are placed on an aging substrate (2) which has been prepared under predetermined bias application conditions.
). Next, the aging board (2) and the DC voltage source (3) are connected with a lead wire (4), and a test tank (5), which is a thermostatic chamber at a predetermined temperature, is placed in a state where a predetermined constant voltage is applied.
). In this way, the test current continues to be applied to the plurality of semiconductor elements (1) all at once under a predetermined environmental condition in the test chamber (5). Thereafter, in order to check for the occurrence of defects, the semiconductor element (1) and the aging substrate (2) are taken out from the test chamber (5) and left to cool at room temperature.
半導体素子（１１が常温になった後直流電圧源（３）の
電圧をＯｖまで下げ、半導体素子（１）をエージング基
板（２）から取シ外し、ＩＣテスタで個々に不良の有無
を検査する。その後更に試験を継続する場合は上述の内
容を繰返す。After the semiconductor element (11) has reached room temperature, lower the voltage of the DC voltage source (3) to Ov, remove the semiconductor element (1) from the aging board (2), and inspect it individually for defects using an IC tester. .If you wish to continue the test, repeat the above steps.
従来の試験方法は以上のようになされているので、不良
半導体素子の有無等を検査するために。Conventional testing methods are performed as described above, and are used to test for the presence or absence of defective semiconductor elements.
所定時間毎に一旦試験を中断しなければならず。The test must be temporarily interrupted at specified intervals.
試験を再開する迄に数時間必要であった。特に短時間で
不良が発生するような半導体素子の試験では、この試験
、中断検査、再開の作業を頻繁に繰返さねばならず、試
験が繁雑で非常に長時間を要し、−！た不良にいたった
正確な時間が観測できないなどの問題点があった。It took several hours before the exam could be resumed. Particularly when testing semiconductor devices where defects occur in a short period of time, this test, interruption inspection, and restart operations must be repeated frequently, making the test complex and extremely time-consuming. There were problems such as the inability to observe the exact time when the failure occurred.
この発明は上記のような問題点を解決するためになされ
たもので、試験を中断することなく、試験状態のま＼で
、不良半導体素子の発生を検出できるとともに、不良に
いたった正確な時間が観測できる半導体装置の信頼性試
験方法を提供することを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to detect the occurrence of a defective semiconductor element in the test state without interrupting the test, and to determine the exact time when the defect occurred. The purpose of this study is to provide a method for testing the reliability of semiconductor devices by which the reliability of semiconductor devices can be observed.
この発明にかかる半導体装置の信頼性試験方法は、直流
電源装置から半導体素子への一括供給電流の時間的経過
を記録する記録器を、上記半導体素子及び直流電源に接
続した状態で、半導体素子を試験槽に投入し試験を行な
うようにしたものである。The reliability testing method for a semiconductor device according to the present invention includes a method for testing the reliability of a semiconductor device by connecting a recorder for recording the elapsed time of a current supplied to the semiconductor device from a DC power supply to the semiconductor device and the DC power source. It is designed to be put into a test tank and tested.
この発明における半導体装置の信頼性試験方法は、半導
体素子への一括供給電流の変化を記録器に記録させてお
き、その記録を観測することＫより、一括供給電流の変
化時点、変化回数で半導体素子の不良発生時点２個数な
どを知ることができる。The reliability test method for a semiconductor device according to the present invention is to record changes in the bulk supply current to the semiconductor element in a recorder and observe the record. It is possible to know the number of elements at the time of failure.
それで試験の途中で一々半導体素子を試験槽から取出し
検査しなくても、半導体素子の不良発生時点２個数を観
測することが可能となった。Therefore, it is now possible to observe the number of semiconductor devices at two points in time when defects occur, without having to take each semiconductor device out of the test chamber and inspect it during the test.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例を説明するだめの図で９図
において、（１）〜（５）は第２図の同一符号と同一部
分を示し、（６）は直流電源装置（３）からエージング
基板（２）に供給される半導体素子一括試験電流を検出
するための抵抗器、（７）はこの抵抗器（６）の電圧降
下の時間的経過を記録する記録器である。FIG. 1 is a diagram for explaining one embodiment of the present invention. In FIG. 9, (1) to (5) indicate the same parts with the same reference numerals as in FIG. ) is a resistor for detecting the semiconductor element batch test current supplied to the aging board (2), and (7) is a recorder that records the time course of the voltage drop of this resistor (6).
次に、この実施例による試験方法を説明する。Next, a test method according to this example will be explained.
まず、複数の半導体素子（１）をエージング基板（２）
に装着し、このエージング基板（２）と直流電圧源（３
）とを抵抗器（６）を介してリード線（４）で接続し、
半導体素子（１）に一括して所定電圧を印加した状態で
、高温の恒温槽である試験槽（５）に投入する。その後
。First, a plurality of semiconductor elements (1) are placed on an aging substrate (2).
This aging board (2) and DC voltage source (3)
) with the lead wire (4) via the resistor (6),
A predetermined voltage is applied to the semiconductor element (1) all at once, and the semiconductor element (1) is placed in a test chamber (5) which is a high-temperature constant temperature chamber. after that.
半導体素子（１）を含めた試験装置が安定したら、抵抗
器（６）の両端を記録器（７）に接続し抵抗器（６）で
の電圧降下を記録していく。このようにして、試験槽（
５）内での半導体素子（１）への一括試験電流の時間的
経過が記録器（７）によって記録される。それである半
導体素子（１）が不良となると、その素子への電源電流
の増加、或いは入出力のリーク電流の増加をきたすため
、その分生導体素子（１）への一括供給電流は増加する
。それが抵抗器（６）の電圧降下の増加となり記録器（
７）に記録される。これによって半導体素子（１）の不
良にい之った時間が観測できる。その後他の半導体素子
１１Ｊ ｄｉ不良となると抵抗器（６）の電圧降下はさ
らに大きくなるため、その変化の数により不良半導体素
子の奴が観測できる。Once the test equipment including the semiconductor element (1) is stabilized, both ends of the resistor (6) are connected to a recorder (7) and the voltage drop across the resistor (6) is recorded. In this way, the test tank (
5), the time course of the bulk test current to the semiconductor element (1) is recorded by the recorder (7). When the semiconductor element (1) becomes defective, the power supply current to the element increases or the input/output leakage current increases, so that the bulk current supplied to the live conductor element (1) increases. This causes an increase in the voltage drop across the resistor (6) and the recorder (
7) is recorded. This allows the time taken for the semiconductor element (1) to become defective to be observed. If another semiconductor element 11J di becomes defective thereafter, the voltage drop across the resistor (6) becomes even larger, so that the defective semiconductor element can be identified by the number of changes.
なお、上記実施例では高温連続動作試験について示した
が、その他バイアスを印加する信頼性試験においても適
用できる。In addition, although the above-mentioned example shows a high temperature continuous operation test, it can also be applied to other reliability tests in which a bias is applied.
〔発明の効果〕
以上のようにこの祐明によれば半導体素子への一括供給
’に流の時間的経過ケ把録する記録器を接続した状態で
半導体素子を試験槽に投入して試験ケ行なうようにし友
ので、半導体素子を横歪するために中断することなく、
不良半導体素子の発生が、演出でき、不良にい之った正
確な時間が観測できる効果なＭしているＱそのため試験
時間の短媚がはかれる利点をも有して・ハる。[Effects of the Invention] As described above, according to this Yumei, a recorder for recording the time course of the flow is connected to the 'batch supply to the semiconductor elements', and the semiconductor elements are put into the test tank and the test chamber is carried out. So that the semiconductor device can be transversely strained without interruption.
It has the advantage that the occurrence of a defective semiconductor element can be simulated and the exact time it took to become defective can be observed.Therefore, it also has the advantage of shortening the test time.
第１図はこの発明の一実踊例を祝胸するたのの図、第２
図は従来の半畳体装置の信頓性試戚方法を説明するため
の図である。
図において、（１）は半導体素子、（２１はエージング
基板、（３）は直流電圧源、（旬はリード線、（５）は
試験槽、（６）は抵抗器、（７）は記録器である。
図中同一符号は同−或は相当部分を示す。Figure 1 is an illustration of Tanono celebrating an example of the dance of this invention, Figure 2
The figure is a diagram for explaining a conventional method for testing the credibility of a semi-folded body device. In the figure, (1) is a semiconductor element, (21 is an aging board, (3) is a DC voltage source, (is a lead wire, (5) is a test chamber, (6) is a resistor, and (7) is a recorder. The same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
定電圧を印加した状態で試験槽に投入し、その中で所定
のバイアス電圧印加状態で上記半導体素子に一括して試
験電流を流し、その後試験槽から取出し、上記半導体素
子を個別に検査するようにした半導体装置の信頼性試験
方法において、上記直流電源装置から上記半導体素子へ
の一括供給電流の時間的経過を記録する記録器を上記半
導体素子及び直流電源に接続した状態で上記半導体素子
を上記試験槽に投入し試験を行なうようにしたことを特
徴とする半導体装置の信頼性試験方法。A plurality of semiconductor devices are connected to a DC power supply and a predetermined voltage is applied to the test chamber, and a test current is applied to the semiconductor devices at once while a predetermined bias voltage is applied. In a reliability testing method for a semiconductor device in which the semiconductor device is taken out from a test tank and inspected individually, a recorder for recording the time course of a current collectively supplied from the DC power supply to the semiconductor device is attached to the semiconductor device. A reliability testing method for a semiconductor device, characterized in that the semiconductor device is tested by placing it in the test tank while connected to the device and a DC power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25101384A JPS61128541A (en) | 1984-11-27 | 1984-11-27 | Reliability testing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25101384A JPS61128541A (en) | 1984-11-27 | 1984-11-27 | Reliability testing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61128541A true JPS61128541A (en) | 1986-06-16 |
Family
ID=17216335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25101384A Pending JPS61128541A (en) | 1984-11-27 | 1984-11-27 | Reliability testing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61128541A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0724579U (en) * | 1992-08-20 | 1995-05-09 | 株式会社ワンウイル | Vacuum suction pad |
| KR100332133B1 (en) * | 1995-03-14 | 2002-10-25 | 주식회사 하이닉스반도체 | High temperature test method of semiconductor device |
| JP2006278816A (en) * | 2005-03-30 | 2006-10-12 | Jfe Steel Kk | Method for improving semiconductor element characteristic |
-
1984
- 1984-11-27 JP JP25101384A patent/JPS61128541A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0724579U (en) * | 1992-08-20 | 1995-05-09 | 株式会社ワンウイル | Vacuum suction pad |
| KR100332133B1 (en) * | 1995-03-14 | 2002-10-25 | 주식회사 하이닉스반도체 | High temperature test method of semiconductor device |
| JP2006278816A (en) * | 2005-03-30 | 2006-10-12 | Jfe Steel Kk | Method for improving semiconductor element characteristic |
| JP4720248B2 (en) * | 2005-03-30 | 2011-07-13 | Ｊｆｅスチール株式会社 | Thyristor element characteristic improvement method |
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