JPS61209368A - Method for inspecting semiconductor apparatus - Google Patents

Abstract

PURPOSE:To enable the specification of an inferior area, by applying voltage higher than rated voltage to a semiconductor apparatus and comparing the light emitting pattern of an Al-electrode part with that of a standard product. CONSTITUTION:Voltage 1.5 times higher than rated voltage is applied to a semiconductor apparatus. Whereupon, the light emitting pattern of a standard product operated normally is observed in the entire regions of a gate finger 5 but a local light emitting region 6 is observed in an inferior product by the application of low voltage. By comparing the light emitting pattern of the semiconductor apparatus with that of the normally operated standard product by microscopic observation, the specification of an area inferior to voltage resistance is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an inspection method for examining breakdown voltage defects in a semiconductor device using an Al electrode light emitting pattern.

Conventional technology Conventionally, for example, to measure the withstand voltage of a G15S FIT, a curve tracer is used to project the voltage-current characteristics on a display and the voltage value at a specific current value is read, or a constant current power supply is used. There is a method of measuring the potential difference between the junctions using a voltmeter when a specific current is passed through the gate junction in the opposite direction, and this is measured as the withstand voltage of the entire GaAgFIT.

Problems to be Solved by the Invention In such conventional methods, since the withstand voltage of the entire semiconductor device is measured, it is impossible to identify the location where the withstand voltage is defective.

GILA again! A peculiar phenomenon of IFIcs is that the withstand voltage decreases over time during operation, eventually causing a gate disconnection failure. However, with conventional measurement methods, it was not possible to identify the defective location until a gate disconnection occurred.

The present invention has been made in view of this point, and aims to enable identification of defective locations using light emitting patterns and to perform inspection in a short time.

Means for Solving the Problems In order to solve the above problems, the present invention applies a voltage higher than 50% of the rated voltage to the semiconductor device to produce a standard product light emitting pattern that operates normally in the light emitting pattern of the Al electrode part. By comparing the pattern with microscopic observation, locations with voltage resistance defects are identified, and the lot is determined to be non-defective.

According to the present invention, by the method described above, it is possible to identify a location where the breakdown voltage is low due to a defect in a semiconductor element, or to identify a location where the breakdown voltage is decreased in an operating state.

Embodiment FIG. 1 is an external plan view of a GaAsFKT device with a specific light emitting pattern of a standard product that operates normally, and a voltage 2.5 times the rated voltage is applied. (In the figure, 1 is the gate, 2 is the source, 3 is the drain, 4 is the active layer region, 6 is the gate finger, and 6 is the gate light emitting region.) In this way, uniform light emission can be seen in all gate fingers. .

FIG. 2 shows a light emission pattern due to mask displacement, and a voltage twice the rated voltage is applied. Here, due to mask misalignment, light emission is seen at every other gate finger.

Figure 3 shows the light emission at the defective part of the protective film, which is 1.6 of the rated voltage.
Applying twice the voltage. As shown on each side of Figures 1 to 3, in a standard product that operates normally, a light emission pattern is observed over the entire gate finger when a high voltage is applied, whereas in a defective product, a light emission pattern is observed in the entire gate finger when a low voltage is applied. A typical luminescence pattern is observed.

Figure 4 shows changes in various characteristics of the GaAs FIT over time during a high-temperature operation test (channel temperature 250°C), and the withstand voltage gradually decreases, eventually leading to gate disconnection. As shown in FIG. 6, this gate disconnection is due to the generation of a void in a part of the gate finger. Figure 6 shows high temperature storage (337
This is an example of the formation of an intermetallic compound between the M4 electric wire and the M U wire at 10° C.). As a result of this formation reaction, Al migrates into silicon, and voids are generated in the Al [ffl] at distant positions.

From this, it can be concluded that the gate disconnection failure in high-temperature operation tests of GaAs FETs is due to the generation of voids in a part of the gate finger due to the reaction of forming a mu-U-Al intermetallic compound in the gate pad area, and the breakdown voltage deterioration is due to these voids. This is thought to be caused by changes in the Al gate as the process progresses.

Although the gate change cannot be visually discerned at the beginning of the breakdown voltage reduction, the light emission pattern when a voltage twice the rated voltage is applied becomes non-uniform as shown in FIG. From this, it is considered that the gate change occurs at this light emitting position.

The above has been described for the case of GaAs FIT, but the mechanism by which light emission occurs when a voltage higher than the rated voltage is applied is the same in the case of the 81 semiconductor device, so the present invention can also be applied to the 81 semiconductor device. Needless to say.

Effects of the Invention As is clear from the above description, according to the present invention, the cause of breakdown voltage failure can be easily detected and is extremely effective in practice.

[Brief explanation of the drawing]

Figure 1 shows the GaAs FRT device diagram and the light emission pattern of a standard product that operates normally. Figure 2 shows the light emission pattern due to mask misalignment. Figure 3 shows the light emission pattern at a defective part of the protective film. , Fig. 4 is a diagram showing changes in characteristics over time in a high-temperature operation test of GaAs FIET, Fig. 6 is a cross-sectional view of a gate finger of a defective product with gate disconnection that occurred in this test, and Fig. 6 is a diagram showing the relationship between the Al electrode and the MuU wire. Figure 7 shows an example of Al electrode void generation due to the formation of intermetallic compounds.
FIG. 7 is a diagram showing a light emission pattern at an early stage of breakdown voltage reduction in a high-temperature operation test of LAI97IET. 1...Gate, 2...Source, 3...
...Drain, 4...Active layer region, 6...
・・・Gate finger, 6゛°“°°gate light emitting area. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure T Gate Figure 3! Gate Fig. 4 Pout -- 1 output power, 7 ports LIFE TIME (HOLJR5) Fig. 5 Fig. 6/4. /d home pole void

Claims (1)

[Claims] When inspecting semiconductor devices for breakdown voltage defects,
A semiconductor device inspection method characterized by applying a voltage higher than 0% and comparing the light emitting pattern of an Al electrode part with the light emitting pattern of a normally operating standard product by microscopic observation to determine the good quality of a lot. .