JPS62276879A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62276879A JPS62276879A JP11934886A JP11934886A JPS62276879A JP S62276879 A JPS62276879 A JP S62276879A JP 11934886 A JP11934886 A JP 11934886A JP 11934886 A JP11934886 A JP 11934886A JP S62276879 A JPS62276879 A JP S62276879A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- interconnection
- tunneling oxide
- tunnel oxide
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000005641 tunneling Effects 0.000 abstract 6
- 238000012360 testing method Methods 0.000 description 11
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔概要〕
本発明は、半導体集積回路に於いて、配線用パッドの形
成領域の一部にメモリ・セルの構成要素であるトンネル
酸化膜と同時に形成されたそれを有するMISキャパシ
タを形成し且つそのMISキャパシタの特性を測定する
為の電圧を供給する実際の配線を施すことに依り、性能
及び耐久性が良好な半導体集積回路を判定する上で重要
な要素になるメモリ・セルに於けるトンネル酸化膜の膜
厚及び膜質をウェハ段階で容易且つ確実に測定できるよ
うにした。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The present invention provides a semiconductor integrated circuit in which a tunnel oxide film, which is a component of a memory cell, is formed in a part of a region where a wiring pad is formed. By forming an MIS capacitor with the same formed at the same time and by providing actual wiring to supply voltage for measuring the characteristics of the MIS capacitor, it is possible to judge a semiconductor integrated circuit with good performance and durability. The film thickness and film quality of the tunnel oxide film in memory cells, which are important factors in memory cells, can be easily and reliably measured at the wafer stage.
本発明は、トンネル酸化膜を必要とする半導体集積回路
に関する。The present invention relates to a semiconductor integrated circuit that requires a tunnel oxide film.
一般に、EEPROM(electricaleras
able and programmable
read only memory)或いはEEFR
OMとSRAM(static random a
ccess memory)とを組み合わせて不揮発
性化したNVRAM (n o n−volatile
RAM)などに於いては、メモリ・セルとして、例
えば、トンネル酸化膜とフローティング・ゲートを有す
るM I S トランジスタを用い、そのドレインとフ
ローティング・ゲートとの間にトンネル酸化膜を形成す
ることに依ってエレクトロンをドレインからフローティ
ング・ゲートに注入したり、或いは、逆にフローティン
グ・ゲートからドレインに注入して書き込みを行うよう
にしている。In general, EEPROM (electrical
able and programmable
read only memory) or EEFR
OM and SRAM (static random a
NVRAM (non-volatile memory)
In devices such as RAM (RAM), for example, an MIS transistor having a tunnel oxide film and a floating gate is used as a memory cell, and a tunnel oxide film is formed between the drain and the floating gate. Writing is performed by injecting electrons from the drain to the floating gate, or conversely from the floating gate to the drain.
その際、エレクトロンはトンネル酸化膜をトンネ゛1ン
グしてそれぞれの電極に到達するものである6
(発明が解決しようとする問題点〕
前記説明したようにトンネル酸化膜はエレクトロンがト
ンネリングするものであり、従って、その膜厚の均一性
や改質の良否はメモリ・セルの耐久特性や記憶特性に重
大な影響を及ぼすものである。At that time, electrons tunnel through the tunnel oxide film and reach each electrode.6 (Problem to be solved by the invention) As explained above, the tunnel oxide film is one through which electrons tunnel. Therefore, the uniformity of the film thickness and the quality of the modification have a significant influence on the durability and storage characteristics of the memory cell.
ところが、そのようなトンネル酸化膜を製造する工程に
於いて、その制御を完全に行うことは極めて困難であり
、膜厚の不均一や膜質に欠陥が発生する等は回避できな
い現状にあり、しかも、そのような状態にありながら、
メモリ・セルは高々1000 (回]程度の消去/書
き込みテストを経た後は、10’〜105 〔回〕程度
の消去/書き込みに耐えることが必要となる。However, in the process of manufacturing such a tunnel oxide film, it is extremely difficult to completely control it, and it is impossible to avoid uneven film thickness and defects in film quality. , while in such a state,
After a memory cell has undergone an erase/write test of about 1000 times, it is required to endure erase/write tests of about 10' to 105 times.
このような問題を解消するには、ロフト単位での抜き取
りで104〜105 〔回〕程度のテストを行って信頼
度を確認すればよいが、これは、量産工程に於けるウェ
ハの段階では極めて困難な作業である。In order to solve this problem, it is possible to check the reliability by performing a test of about 104 to 105 times by sampling each loft, but this is extremely difficult at the wafer stage in the mass production process. It is a difficult task.
その理由は、ウェハにプローブを長時間に亙り良好な状
態でコンタクトさせておくことが難しいこと、また、例
えば、1回の消去/書き込みに5(ms)の時間が必要
とすると1000回では5(S)であり、従って、1個
のチップについて行うことができる消去/書き込み試験
の上限は前記プローブ・コンタクト問題や前記試験時間
の関係から高々2000回程度となる。そこで、全チッ
プに対し、〜2000回の消去/書き込み試験をして予
め良品と不良品を判別してから、更に、該試験を通過し
た良品群から一部チツブを抜き取って104〜105回
の消去/書き込みを行い、ロット全体の耐久性を保証す
るとなると、試験に大変な長時間を要することになるか
ら工程自体が長時間化してコストが上昇してしまう。The reason for this is that it is difficult to keep the probe in good contact with the wafer for a long period of time, and for example, if one erase/write requires 5 (ms), 1000 times requires 5 (ms). (S) Therefore, the upper limit of the erase/write test that can be performed on one chip is about 2000 times at most due to the probe contact problem and the test time. Therefore, after performing an erase/write test on all chips ~2,000 times to distinguish between good and defective products in advance, some chips were selected from the group of good products that passed the test and tested 104 to 105 times. If the durability of the entire lot is to be guaranteed by erasing/writing, the test will take a very long time, which will lengthen the process itself and increase costs.
本発明は、トンネル酸化膜の膜厚及び膜質をウェハの状
態に於いて監視できるような構成にした半導体集積回路
を提供し、ウェハの段階で不良品を容易且つ確実に排除
できるようにする。The present invention provides a semiconductor integrated circuit configured so that the thickness and quality of the tunnel oxide film can be monitored in the wafer state, thereby making it possible to easily and reliably eliminate defective products at the wafer stage.
本発明に依る半導体集積回路に於いては、半導体チップ
(例えば半導体チップ1)内に形成されてトンネル酸化
膜及びフローティング・ゲートを有するメモリ・セルと
、該メモリ・セルが形成された半導体チップの周辺に配
列された配線用パッド(例えば配線用パッド2)と、該
配線用パッドの形成領域に在って前記トンネル酸化膜と
同時に形成されたそれを有するMrSキャパシタ(例え
ばMISキャパシタ3)と、該M+sキャパシタに於け
るトンネル酸化膜の特性を測定する為に電圧を供給する
配線(例えば引き出し配線8及び9)とを備えた構成に
なっている。In the semiconductor integrated circuit according to the present invention, a memory cell formed in a semiconductor chip (for example, semiconductor chip 1) and having a tunnel oxide film and a floating gate, and a semiconductor chip in which the memory cell is formed, Wiring pads (for example, wiring pads 2) arranged around the periphery, and MrS capacitors (for example, MIS capacitors 3) having the pads located in the formation area of the wiring pads and formed at the same time as the tunnel oxide film; The configuration includes wires (for example, lead wires 8 and 9) for supplying voltage in order to measure the characteristics of the tunnel oxide film in the M+s capacitor.
前記手段を採ることに依り、半導体集積回路の性能及び
耐久性が良好であるか否かを判定する上で重要な要素に
なるメモリ・セルに於けるトンネル酸化膜の膜厚及び膜
質をウェハの段階で容易且つ確実に測定できるものであ
る。By adopting the above method, the thickness and quality of the tunnel oxide film in the memory cell, which is an important factor in determining whether the performance and durability of the semiconductor integrated circuit are good, can be evaluated on the wafer. It can be easily and reliably measured in stages.
第1図は本発明一実施例の要部平面図を表している。 FIG. 1 shows a plan view of essential parts of an embodiment of the present invention.
図に於いて、1は半導体チップ、2は配線用パッド、3
はトンネル酸化膜を用いたMISキャパシタ、3AはM
ISキャパシタと配線用パッドとを結ぶ配線をそれぞれ
示している。In the figure, 1 is a semiconductor chip, 2 is a wiring pad, and 3 is a semiconductor chip.
is an MIS capacitor using tunnel oxide film, 3A is M
Wiring connecting the IS capacitor and the wiring pad is shown.
第2図は第1図に見られるMISキャパシタ部分の要部
切断側面図を表している。FIG. 2 shows a cutaway side view of the main part of the MIS capacitor part seen in FIG. 1.
図に於いて、4はシリコン半導体基板、5はMIsキャ
パシタに於ける一方の電極となる不純物導入領域、6は
トンネル酸化膜、7はMI Sキャパシタに於ける他方
の電極、8は配線用パッドに接続されてトン皐ル膜試験
電圧VTEST (例えば13〔V〕)が印加される引
き出し配線、9は例えば負側電源電圧VSSを供給する
パッドに接続される引き出し配線をそれぞれ示している
。尚、トンネル酸化膜6は、他のメモリ・セルを構成す
る為のトンネル酸化膜と同時に形成したものであること
は勿論である。In the figure, 4 is a silicon semiconductor substrate, 5 is an impurity doped region that becomes one electrode of the MIS capacitor, 6 is a tunnel oxide film, 7 is the other electrode of the MIS capacitor, and 8 is a wiring pad. Reference numeral 9 denotes a lead wire connected to a pad to which a voltage test voltage VTEST (for example, 13 [V]) is applied, and a lead wire 9 connected to a pad that supplies, for example, a negative power supply voltage VSS. Incidentally, the tunnel oxide film 6 is, of course, formed at the same time as the tunnel oxide films for forming other memory cells.
本発明では、図示例に見られるように、半導体集積回路
に於ける配線用パッド形成領域の少なくとも一つにM
I Sキャパシタ3を形成して、その一方の電極の役目
を果たす不純物導入領域5は引出し配線9を介して負側
電源電圧VSSを供給するパッド(図示せず)に接続し
、また、その他方の電極7は引出し配線8を介して配線
用パッド2と接続する。尚、不純物領域5の引出し配線
9は負側電源電圧VSS用のパッドに接続せずに独立さ
せておいてもよい。In the present invention, as shown in the illustrated example, M
An impurity-doped region 5 that forms the IS capacitor 3 and serves as one electrode thereof is connected to a pad (not shown) that supplies a negative power supply voltage VSS via an extraction wiring 9, and the other The electrode 7 is connected to the wiring pad 2 via a lead wiring 8. Note that the lead wire 9 of the impurity region 5 may be left independent without being connected to the pad for the negative power supply voltage VSS.
このように、MISキャパシタ3を実際に配線し、ウェ
ハ段階のテストで電流−電圧特性や耐圧を測定して標準
値と比較し、トンネル酸化膜6の良否、従って、メモリ
・セル全体に於けるトンネル酸化膜の良否をモニタする
。尚、測定が終了したならば、MISキャパシタ3に公
称耐圧以上の電圧を次第に高めながら印加して破壊し、
最高耐圧を知得するなどは任意である。In this way, the MIS capacitor 3 is actually wired, and the current-voltage characteristics and breakdown voltage are measured in a test at the wafer stage and compared with standard values to determine the quality of the tunnel oxide film 6 and, therefore, the overall memory cell. Monitor the quality of the tunnel oxide film. When the measurement is completed, a voltage higher than the nominal withstand voltage is gradually applied to the MIS capacitor 3 to destroy it.
Knowing the maximum withstand voltage is optional.
前記説明したようなM I Sキャパシタ3はウェハ内
の全チップに設けられているから、それ等について測定
を行って平均や偏差を解析することに依って、ウェハ内
に於けるトンネル酸化膜の膜厚及び膜質の分布を容易且
つ確実に判定することができ、また、ロソI−評価も同
様に行なえるから、その結果、ロフトの出荷判定を行う
ことも可能である。Since the MIS capacitors 3 as described above are provided on all chips within the wafer, by measuring them and analyzing the average and deviation, it is possible to determine the tunnel oxide film within the wafer. Since the distribution of film thickness and film quality can be easily and reliably determined, and Roso I-evaluation can be performed in the same way, it is also possible to determine the loft for shipping.
本発明に依る半導体集積回路に於いては、配線用ハツト
の形成領域の一部にメモリ・セルの構成要素であるトン
ネル酸化膜と同時に形成されたそれを有するMISキャ
パシタを形成し且つそのMISキャパシタの特性を測定
する為の電圧を供給する実際の配線を施す構成になって
いる。In the semiconductor integrated circuit according to the present invention, a MIS capacitor having a tunnel oxide film which is a constituent element of a memory cell is formed in a part of the wiring hatch formation region, and the MIS capacitor is The configuration is such that the actual wiring is used to supply the voltage for measuring the characteristics of the device.
前記構成を採ることに依り、半導体集積回路の性能及び
耐久性が良好であるか否かを判定する上で重要な要素に
なるメモリ・セルに於けるトンネル酸化膜のI1g厚及
び膜質をウェハの段階で容易且つ確実に測定できるもの
である。By adopting the above configuration, the I1g thickness and film quality of the tunnel oxide film in the memory cell, which are important factors in determining whether the performance and durability of the semiconductor integrated circuit are good, can be determined on the wafer. It can be easily and reliably measured in stages.
第1図は本発明一実施例の要部平面図、第2図は同しく
要部切断側面図を表している。
図に於いて、1は半導体チップ、2は配線用パッド、3
はトンネル酸化膜を用いたMISキャパシタ、3AはM
ISキャパシタと配線用パッドとを結ぶ配線、4はシリ
コン半導体基板、5はMISキャパシタに於ける一方の
電極となる不純物導入領域、6はトンネル酸化膜、7は
MISキャパシタに於ける他方の電極、8は配線用パッ
ドに接続されてトンネル膜試験電圧V TESア(例え
ば13〔V])が印加される引き出し配線、9は例えば
負側型a電圧VSSを供給するパッドに接続される引き
出し配線をそれぞれ示している。
実施例の要部平面図
第1図FIG. 1 is a plan view of a main part of an embodiment of the present invention, and FIG. 2 is a cutaway side view of the main part. In the figure, 1 is a semiconductor chip, 2 is a wiring pad, and 3 is a semiconductor chip.
is an MIS capacitor using tunnel oxide film, 3A is M
Wiring connecting the IS capacitor and the wiring pad, 4 is a silicon semiconductor substrate, 5 is an impurity-introduced region that becomes one electrode in the MIS capacitor, 6 is a tunnel oxide film, 7 is the other electrode in the MIS capacitor, Reference numeral 8 designates a lead wire connected to a wiring pad to which a tunnel film test voltage VTESA (for example, 13 [V]) is applied; 9 designates a lead wire connected to a pad that supplies, for example, a negative side type a voltage VSS. are shown respectively. Fig. 1 Plan view of main parts of the embodiment
Claims (1)
ティング・ゲートを有するメモリ・セルと、 該メモリ・セルが形成された半導体チップの周辺に配列
された配線用パッドと、 該配線用パッドの形成領域に在って前記トンネル酸化膜
と同時に形成されたそれを有するMISキャパシタと、 該MISキャパシタに於けるトンネル酸化膜の特性を測
定する為に電圧を供給する配線とを備えてなることを特
徴とする半導体集積回路。[Scope of Claims] A memory cell formed in a semiconductor chip and having a tunnel oxide film and a floating gate; Wiring pads arranged around the semiconductor chip in which the memory cell is formed; and the wiring. an MIS capacitor formed at the same time as the tunnel oxide film in a region where the tunnel oxide film is formed, and wiring for supplying a voltage to measure the characteristics of the tunnel oxide film in the MIS capacitor. A semiconductor integrated circuit characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11934886A JPS62276879A (en) | 1986-05-26 | 1986-05-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11934886A JPS62276879A (en) | 1986-05-26 | 1986-05-26 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62276879A true JPS62276879A (en) | 1987-12-01 |
Family
ID=14759264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11934886A Pending JPS62276879A (en) | 1986-05-26 | 1986-05-26 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62276879A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0231465A (en) * | 1988-07-21 | 1990-02-01 | Sony Corp | Non-volatile memory wafer |
JPH05243359A (en) * | 1990-04-16 | 1993-09-21 | Natl Semiconductor Corp <Ns> | Ferroelectric capacitor test structure for chip die |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5548947A (en) * | 1978-10-05 | 1980-04-08 | Toshiba Corp | Evaluation of semiconductor integrated circuit |
JPS6130044A (en) * | 1984-07-20 | 1986-02-12 | Nippon Denso Co Ltd | Semiconductor chip inspection method |
-
1986
- 1986-05-26 JP JP11934886A patent/JPS62276879A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5548947A (en) * | 1978-10-05 | 1980-04-08 | Toshiba Corp | Evaluation of semiconductor integrated circuit |
JPS6130044A (en) * | 1984-07-20 | 1986-02-12 | Nippon Denso Co Ltd | Semiconductor chip inspection method |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0231465A (en) * | 1988-07-21 | 1990-02-01 | Sony Corp | Non-volatile memory wafer |
JPH05243359A (en) * | 1990-04-16 | 1993-09-21 | Natl Semiconductor Corp <Ns> | Ferroelectric capacitor test structure for chip die |
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