JPS5937866Y2 - semiconductor IC memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor IC memory in which an abnormality in a memory power supply system can be discovered as early as possible in the memory manufacturing process.

The power supply current test for an IC memory in which a memory cell section and peripheral circuit sections such as a decoder and an address buffer are formed on a chip and the chip is housed in a package includes a room temperature test and a high temperature test.

At the early stage of the memory manufacturing process, the chips are not scribed into the casing and are formed into multiple sections on the wafer. However, high-temperature tests are difficult in this wafer state, so power supply system tests are usually conducted at room temperature with power supply terminals. This is done by applying a voltage to the circuit and measuring the current flowing through it.

The wafer is then scribed onto each chip, and each chip determined to be non-defective in the room temperature test is housed in a package to become an IC memory, and a high temperature test is performed in this state.

In this way, in order to increase the yield of IC memories that are ultimately determined to be non-defective products after going through room temperature and high temperature tests, more stringent checks must be carried out during the room temperature tests, and chips that would be defective in the high temperature tests must be checked. It is necessary to eliminate wasteful steps such as putting the product into a package.

However, even if a product is determined to be good in a room temperature test, it may actually be defective, or may be inconvenient in terms of reliability.

Specific examples are shown in the table below. In parentheses, the left side is the chip's peripheral circuit current, and the right side is the memory cell current.

Comparing the above specific example between a good product and a defective product C,
In the normal temperature test, both products were judged to be good because they were 70mA, which is within the allowable value (10mA) for the standard non-defective product a, but in the high temperature test, the non-defective product was 70mA.
Since the mA of the defective product C is 80mA, the defective product C is determined to be defective for the first time at this stage.

As can be seen from the above, one reason why practical inconveniences occur during testing is that there is a significant imbalance between the proportions of the peripheral circuit section current and the memory cell section current in the total power supply current.

Even though the power supply current is 60 mA for the remaining good product A, the current in the memory cell portion is only about 1 mA, and the remaining 59 mA is the current in the peripheral circuit portion.

Therefore, by setting the allowable value to 10 mA, and measuring the power supply current, it is found that the chip is good and the defective product C is 70mA, so of course the chip is good, but like the defective product C, its standard value is 60mA.
If all of the excess 10 mA from the memory cell section is assumed to be from the memory cell section, the memory cell section is consuming more than 10 times the current of the standard state, which is clearly abnormal.

If the power supply current value of the memory cell section and the power supply current value of the peripheral circuit section could be known separately, this type of abnormality could be easily discovered, and defective chips could be detected at the earliest possible stage of the memory manufacturing process. By taking appropriate measures, residual damage can be minimized.

However, in conventional IC memory, only one power supply terminal (ponding pad) inside the chip, which is connected to the external power supply terminal (pin) of the package by wire etc., is provided in both the memory cell part and the peripheral circuit part. However, it is impossible to measure only the current flowing in the memory cell section or the current flowing in the waveside circuit section, and of course it is not possible to estimate the proportion thereof.

The present invention attempts to improve this point by forming a memory cell section in which a plurality of static memory cells are arranged in a matrix and a peripheral circuit section on a semiconductor chip, and housing the chip in a package. In a semiconductor IC memory, a memory cell power supply pad that supplies power to the memory cell portion of the chip and a peripheral circuit power supply pad that supplies power to the peripheral circuit portion are independently provided in the chip, and the memory cell portion The current consumption in the chip and the current consumption in the peripheral circuit section can be measured before the chip is housed in the package, and one power supply terminal of a plurality of terminal pins attached to the package is provided. This device is characterized in that a circuit that enables power supply from the pin to the pads is connected between the pin and the two pads, and this will be explained in detail below with reference to the drawings.

FIG. 1 is a schematic plan view of an IC memory showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of its essential parts.

In FIG. 1, 2 is a memory cell section consisting of a large number of static memory cells arranged in a matrix, 4 is a decoder for selecting a specific cell in the memory cell section, peripheral circuits such as an address buffer, and 8.10 is a pad. These are provided on the semiconductor chip SC.

6 is an external power supply terminal (pin) provided on the package PG
It is.

The chip SC and the package PG are as shown in FIG. 5, and four parts are formed in the base part of the package PG, and the chip SC is accommodated and fixed in the recessed part.

A predetermined number of terminal pins 6 (a predetermined number are arranged on both edges of the package PG, and a lid is placed on the base part (not shown), and the chip S
Seal C.

In the present invention, such an IC memory chip is provided with two independent power supply terminals (ponding pads).

8 and 10 are those. One pad 8 is for the memory cell section, and is connected to the memory cell section 2 by a wiring 12 made of aluminum or the like.

The other pad 10 (used for the peripheral circuit section) is connected to the peripheral circuit section 4 by a wiring 14.

These wiring lines 12, 14, and 14 are formed on the chip at the same time as the wiring of the memory cell portion and/or the peripheral circuit portion.

The pads 8, 10 and the terminal pins 6 are connected by wire bonding after the chip is mounted on the package as shown in FIG.

16 and 18 are the wires, and when this connection is made, pads 8 and 10 become electrically integrated.

One memory power supply terminal appears to be one from the outside of the repackage, and is the same as the conventional one.

However, when the chip is not mounted on the package, and when the chip is not separated from the housing or the chip, the pads 8 and 10 are independent of each other and are not electrically connected to each other.

Figure 2 shows the main part of the memory cell section 2, and each memory cell MC is a MOS that constitutes the main part of a Noritsu flop.
Transistor Q 1 t Q 2 % Load resistor (-! or transistor) R1tR2 and word line (not shown)
The transfer gate selected by Q3. Consisting of Q4,
Cells MC, MC in one column... are pit lines BL, B
Share L.

Although word lines are not shown, they run perpendicular to bit lines BL and BL, and are connected to transnor gates Q3. Q4...
Connected to the gate of...

The pad 8 is connected to each memory cell MC by a wiring 12 as shown in the figure, and supplies power to each cell.

Figure 4 is a schematic plan view of the memory chip, showing the MC8&'j memory cell section, WD a word decoder, SA a sense amplifier, CD a column decoder, AB an address buffer, and D
is the data input/output section.

Pads 8, 10 are provided at appropriate locations around the periphery of such a chip.

In this memory, as described above, the wires 16 and 18 are not provided at the stage before assembly, so the electrodes 8 and 10 are separated.

Therefore, the current in only the memory cell section 2 can be checked by applying a probe to the memory power supply electrode 8.

Even if the current consumption of the whole chip is 60 mA, the current of the memory cell section 2 is small, less than 1 mA, but if the present invention is used, this value can be known reliably and whether it is normal or abnormal can be determined.

Note that it is difficult to perform high-temperature tests during wave probing tests, so it is not possible to actually measure memory current consumption under high-temperature conditions, but if the value at room temperature is known, it will be possible to estimate normality and abnormality at high temperatures more accurately than before. is possible.

It is unlikely that a product with an excessive current value in the room temperature test would improve at high temperatures, so there is no problem in immediately determining that the product is defective based on the room temperature test results.

Incidentally, if the wires 16 and 18 in FIG. 1 are replaced with the other embodiment shown in FIG. 3, only one wire is required.

1. When manufacturing the device, prepare the wiring between 12° and 14° (pad 8
, 10) is inserted with a diode-connected MOS transistor Q5.

The polarity is such that current flows from pad 10 to pad 8, but does not flow in the opposite direction.

In this way, since the pad 10 is electrically conductively isolated when viewed from the pad 8, it is possible to measure the power supply current only in the memory cell portion by applying a glove to the pad 8, and the same effect as in the previous embodiment can be obtained. It will be done.

If the external power supply terminal 6 and the pad 10 are connected with the wire 18 during assembly, power supply current is supplied not only to the peripheral circuit section 4 but also to the memory cell section 2 via the forward diode Q5.

However, in this case, the power supply voltage on the memory cell section 2 side is reduced by the forward drop of the diode Q5.

As described above, according to the present invention, since the current of only the memory cell portion can be measured separately, there is an advantage that it is possible to more reliably determine whether the IC memory is good or bad and can be checked at an early stage of manufacturing.

[Brief explanation of the drawing]

1 and 2 are a schematic plan view and a circuit diagram of a main part showing one embodiment of the present invention, FIG. 3 is a circuit diagram of a main part showing another embodiment of the invention, and FIG. 4 is a diagram of a memory chip. FIG. 5 is a schematic plan view and a schematic cross-sectional view of the IC memory. In the figure, 2 is a memory cell section, 4 is a peripheral circuit section, 6 is an external power supply terminal, 8 is a memory power supply pad, 10 is a peripheral circuit power supply pad, and 16.18 is a wire.

Claims (1)

[Scope of utility model registration request] A semiconductor IC in which a memory cell section in which a plurality of static memory cells are arranged in a matrix and a peripheral circuit section are formed on a semiconductor chip, and the chip is housed in a package.
In a memory, a memory cell power supply pad that supplies power to the memory cell section of the chip and a peripheral circuit power supply pad that supplies power to the peripheral circuit section are provided independently to reduce the consumption in the memory cell section. The structure is such that the current and the current consumption in the peripheral circuit section can be measured before the chip is housed in the package, and one power supply end supply pin and two of the plurality of terminal pins attached to the package are provided. A semiconductor I characterized in that a circuit that enables power supply from the pin to the pad is connected between the two pads.
C memory.