JPH04322441A - Semiconductor integrated circuit device, its inspecting method and inspecting device for use therein - Google Patents

Abstract

PURPOSE:To complete a memory test in a short time by standing a small number of probe pins on all chips, thus inputting a self-test start signal from one of the pins for each chip, and simultaneously executing the test for all the chips. CONSTITUTION:An integrated circuit wafer 3 having many memory chip regions is placed on a test stage 2, and outer test terminals 4 of the number of half or less of the number of outer pins of the respective chips after assembling are brought into contact with substantially all of the chips to be tested of the many chips. A DC test start signal is input from an outer test terminal 7 for at least one test start signal of a plurality of the terminals 4 in contact with the chips in this state, and desired DC characteristics are measured based on a DC start signal. Thus, the entire wafer of the wafer in which highly integrated memory chips, etc., are integrated, can be tested in a high throughput.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to testing techniques such as electrical characteristic testing of semiconductor integrated circuit devices.

0002

2. Description of the Related Art Conventional technologies that may be related to the present application include the following. That is, the wafer (W
Probe test (Probe Te)
st), Test Burn-i
n) or Aging Test
), Japanese Patent Application No. 1-117
No. 461, JP-A-59-99733, JP-A No. 62-14
No. 3436, No. 60-167343, No. 62-221
No. 126, No. 62-287637, No. 62-2936
No. 29, No. 63-204621, No. 64-18233
There are numbers etc. For example, the above-mentioned Japanese Patent Application Publication No. 62-28763
No. 7 has a dynamic burn-in (dynamic burn-in) for the entire wafer by providing a test signal generation circuit on the wafer.
A self-test technique that allows dynamic burn-in is disclosed.

[0003] Furthermore, in order to improve the throughput of probing, a probe card (probe card) is used.
Japanese Utility Model Publication No. 62-98234 and No. 60-12573 are examples of devices that allow the Card) to retain various functions.
No. 6, JP-A No. 1-95529, etc. For example, in the Japanese Patent Application Publication No. 62-123732, there is a prober (P
Speed up probe tests by simplifying signal exchange between the main body (rober) and the probe card (Sp
A probe card has been disclosed in which the test circuit of the prober body is moved to the probe card side in order to improve the quality of the probe.

[0004] In addition to the above, Japanese Patent Application Laid-Open No. 2-170069 and JP-A-2-170069 provide additional functions such as self-testing or test result storage to the wafer or chip that is the object to be inspected for the same purpose. No. 2-3948, same 1-
No. 169938, JP-A-64-8637, JP-A No. 61-
No. 156747, No. 61-12000, No. 60-31
No. 35, No. 58-96744, etc. For example, Japanese Patent Application Laid-Open No. 64-8637 discloses a wafer in which a non-volatile memory is formed on the wafer in order to omit marking after wafer testing.

[0005] Furthermore, Japanese Patent Application Laid-Open Nos. 64-39039 and 59-100 disclose methods for setting the chip, etc. to test mode (Test Mode) by adjusting the timing of input signals to the chip, etc. to be tested.
There are No. 99269, etc.

[0006] Further, there is a probe needle using a shape memory alloy as disclosed in Japanese Patent Application Laid-Open No. 1-282466.

Furthermore, TAB (Tape) is attached to the probe card.
Japanese Patent Application Publication Nos. 59-141239 and 54-1 utilize automated bonding (Automated Bonding) technology.
There are issues such as No. 6183.

[0008]

[Problems to be Solved by the Invention] However, these techniques have not been applied in practice to so-called wafer testing of wafers on which a large number of highly integrated memory chips, etc. are integrated.
throughput).

[0009] Accordingly, one object of the present invention is to enable high throughput testing of all wafers in which a large number of highly integrated memory chips and the like are integrated.

0010

[Means for Solving the Problems] One of the outlines of the present invention for achieving the above object is briefly explained as follows.

That is, this is an electrical testing technique for semiconductor integrated circuit devices in which a large number of memory chips formed on the wafer are self-tested at the same time during the wafer test, and a pass/fail judgment is made on the wafer.

0012

[Operation] That is, according to the above configuration, when performing a wafer test of a highly integrated memory, by setting up a small number of probe pins on almost every chip, a self-test start signal can be inputted from one of the pins for each chip. By executing the test on all chips at once, the memory test can be completed in a short time.

[0013]

[Examples] Specific examples will be described below. Identical reference numerals in these embodiments and figures indicate identical or similar functions. However, this does not apply if it is specifically stated to the contrary.

(1) Example 1 FIG. 1 shows a wafer test of the present invention.
) is an explanatory side view of the prober. In the figure, 1 is a prober, 2 is an XY moving stage or XY stage for moving and aligning the wafer to a predetermined test position, 3 is a wafer to be measured, and 4 is from several hundred to several thousand pieces. Probe pin (P
5 is a probe card that supports the probe pin, 6 is an interface bus that connects the tester and the probe card.
, 7 is a probing test.
t) A tester including a control circuit.

FIG. 2 is a perspective view showing the main part of the test state of the present invention. In the figure, reference numeral 8 denotes a multilayer power signal wiring for interconnecting the probe pins and the interface bus.

FIG. 3 is a schematic front sectional view of the probe card 5. As shown in FIG.

FIG. 4 is a top view showing one chip area out of a large number of chip areas on the wafer 3 to be measured. In the figure, 10 is a memory chip to be measured, and 11 is a memory mat (
12 is a peripheral circuit, 13 is a bonding pad used for testing the present invention.
ing Pad). These five pads will be referred to as "specific pads" hereinafter. These bonding pads are the power supply terminals for Vcc and Vss, RAS￣ and Dout.
It consists of a normal signal terminal and a test signal terminal specified by TS. Of these terminals, the terminals other than TS form part of the external pins after assembly. Regarding the TS terminal, in this embodiment, a case will be described in which there is no corresponding external pin after assembly, but it is also possible to make it correspond to any external pin. The number of these external pins is, for example, 18 pins in a 4M×1 type DRAM.

FIG. 5 shows the layout of the test circuit provided on the above chip for testing the present invention.
) is a top view of the chip. In the same figure, 2
0 is a self-test circuit.

FIG. 6 shows a semiconductor device manufacturing process (Pro
FIG. 2 is a process flow diagram showing the position of the present invention in the process. In the figure, 31 is a wafer process for semiconductor integrated circuits, 32 is a DC test process for electrically testing the DC characteristics of each chip in the wafer state, and 33 is also for electrically testing the AC characteristics and other characteristics of each chip in the wafer state. 34 is a wafer test process for testing, 35 is a wafer dividing process for dividing the wafer into individual chips by dicing, and 36 is for attaching leads to the chips.
d) Packaging such as sealing by attaching etc.
37 is a selection test step in which an electrical characteristic test similar to the wafer test is performed on the assembled chip unit.

FIG. 7 shows a DRAM (Dynamic RAM) according to the present invention.
Random Access Memory)
FIG. In the same figure, RAS￣ is a row address strobe (Row Address strobe).
robe) signal, CAS￣ is the column address strobe (Column Address strobe) signal.
e) Signal WE￣ is write-enable (Write
The Enable) signal and TS are test signals for starting the wafer test of the present invention.

FIG. 8 is a memory circuit block diagram showing the circuit configuration of the chip area of the DRAM of the present invention. In the figure, 41 is a unit chip area, and 42 is a memory matrix in which a large number of memory cells are integrated.
The area 43 is an X decoder for allocating row address signals to corresponding word lines.
r), 44 is a Y decoder for allocating column address signals to corresponding data lines.
, 45 is an address buffer for distributing row and column address signals transferred twice in an address multiplex type to the row address decoder and column address decoder, respectively.
), 46 is a clock generator for generating internal timing signals necessary for normal operation, refresh operation, test operation (including self-test), etc. from signals such as RAS and CAS.
47 is a program counter for counting all the bits to be tested.
ter), 48 is a refresh counter (Refresh C
49 is a data generator for generating various data patterns for testing.
50 is a test control circuit and pattern ROM for controlling the self-test operation of the present invention and generating test patterns, and 51 is for reading and writing data to and from memory cells in various operation modes. write/read circuit, 52
is a determination circuit for determining whether or not data written and data read out match each other during a test operation.

FIG. 9 shows a part of the pattern ROM.
FIG. 3 is a ROM pattern diagram illustrating the contents of a pattern.

Next, the procedure for implementing the present invention will be explained based on these figures. First, a Si wafer 3 (for example, an 8-inch wafer) on which the wafer process 31 (FIG. 6) has been completed (including almost completed) is placed on the test stage 2 as shown in FIG. The upper surface of this Si wafer includes several hundred unit chip areas. Next, as shown in FIG.
The probe pin 4 is applied to the probe pin 4 to maintain electrical contact. In this state, the tester 7 supplies a first activation signal corresponding to the self-test activation procedure to each chip through the plurality of specific pads. First, with power supplied to each chip, the tester 7 measures whether the standby current consumption of each chip in a standby state is within a predetermined range (first DC test). These test results are stored in the test result memory of the tester 7. For each chip whose standby current is normal, the tester sends out a second activation signal for the next test via the plurality of specific pads so as to proceed to the next step. Each chip that receives this second activation signal is automatically put into a write state, and while a certain write operation is being repeated, the current consumption during operation is measured by the tester 7 via the Vcc and Vss power supply terminals. (second DC test). This test result is stored in the test result memory of the tester as above. If the value of the current consumption during operation is within a predetermined range, the tester 7 will measure RAS￣ and TS at the timing shown in FIG.
A third activation signal is sent via the terminal. Based on this third activation signal, each chip sequentially generates timing signals such as CAS and WE within each chip, as shown in FIG. 7, and executes an AC function test of a predetermined test pattern. The test pattern is shown in Figure 9.
ng Pattern). In addition, the test pattern is not limited to marching, but also checkerboard (Che
cker board) etc. can also be selectively implemented. The results of these various pattern tests are judged by the judgment circuit 52 as shown in FIG. is sent from the terminal to the test result memory of the tester,
It will be stored there. Thereafter, each chip is automatically reset internally as shown in FIG.

Further, the circuit operation will be explained based on FIGS. 7 and 8. The test control circuit sets the chip in a standby state based on the first activation signal input from the TS terminal and the RAS terminal. When the measurement of the standby power supply current is completed in this state, the tester 7 connects the TS terminal and the RA terminal.
A second activation signal is input via the S￣ terminal. Based on this signal, the test control circuit 50 controls the program counter 47, refresh counter 48, data generator 49, and others to set a certain writing state. In this state, the power supply current during operation is measured. Further, as shown in FIG. 7, a clock generator 46 receives a third activation signal via the TS terminal and the RAS terminal.
generates timing signals such as CAS￣ and WE￣. On the other hand, the pattern ROM 50 generates a desired test pattern based on the activation signal. Further, the program counter 47 sequentially counts up all bits of the memory under test. Addresses are sequentially generated by the refresh counter 48. Data is similarly generated from the data generator in response to the address. Pass/fail judgment of these results is carried out by the judgment circuit 52 for each bit at the time of reading, and when all the data match, a pass signal is passed, and when even one data does not match, a fail signal is sent to the above D.
It is sent from the out terminal and stored in the test result memory of the tester 7. Test control circuit 50 then sets the chip in a reset state and completes the self-test.

[0025]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are as follows.

That is, when testing a wafer of highly integrated memory, by setting up a small number of probe pins on almost all chips, and inputting a self-test start signal from one of the pins for each chip, all chips can be tested at once. By executing the test, the memory test can be completed in a short time.

[0027] As described above, the technical field that is the background of the present invention,
That is, although the memory test has been described, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist of the present invention. For example, a microcomputer
) IC, Logic IC, Linear (Lin)
It can also be applied to ear) IC, etc.

[Brief explanation of drawings]

FIG. 1 is an explanatory side view of a prober showing the state of a wafer test according to the present invention.

FIG. 2 is a perspective view showing a main part of the test state of the present invention.

FIG. 3 is a schematic front sectional view of the probe card.

FIG. 4 is a top view showing one chip area among a number of chip areas on a wafer to be measured.

FIG. 5 is a top view of the chip showing the layout of a test circuit provided on the chip for testing the present invention.

FIG. 6 is a process flow diagram showing the position of the present invention in the manufacturing process of a semiconductor device.

FIG. 7 is a waveform diagram of the DRAM of the present invention.

FIG. 8 is a memory circuit block diagram showing the circuit configuration of the chip area of the DRAM of the present invention.

FIG. 9 is a ROM pattern diagram illustrating the contents of some ROM patterns of a pattern ROM.

[Explanation of symbols]

1... Prober, 2... XY stage, 3... Wafer to be measured,
4...Probe pin, 5...Probe card, 6...Interface bus, 7...Tester, 8...Multilayer power signal wiring, 1
0... Chip under test, 11... Memory mat, 12... Peripheral circuit, 13... Bonding pad, 20... Self test circuit, 31... Wafer process, 32... DC test, 33...
AC test, 34...Wafer test, 35...Wafer division,
36... Assembly, 37... Sorting test, 41... Chip area, 4
2... Memory matrix, 43... X decoder, 44... Y decoder, 45... Address buffer, 46... Clock generator, 47... Program counter, 48... Refresh counter, 49... Data generator, 50... Test control circuit and pattern ROM, 51 ...Writing/reading circuit, 52... Judgment circuit.

Claims (9)

[Claims] 1. A method for electrically testing a semiconductor integrated circuit memory device wafer comprising the following steps: (a) testing a large number of memory chip areas that have completed a wafer process for forming semiconductor integrated circuit memory devices on a semiconductor wafer; (b) For almost all of the chips to be tested among the large number of memory chips, the number of external pins of each chip is less than half the number of external pins of each of the chips after assembly. Step of bringing the external test terminal into contact; (c) Applying a DC test start signal from at least one test start signal external test terminal among the plurality of external test terminals brought into contact with each of the chips in the state of (b) above. (d) automatically setting each of the chips to a predetermined operating state necessary for the test based on the DC test start signal; (e) the predetermined step of (d) above; Desired DC in operating condition
The process of measuring a property. 2. The method of electrically testing a semiconductor integrated circuit memory device wafer according to claim 1, wherein said desired DC characteristic is power consumption or current consumption of each of said chips. 3. The semiconductor device according to claim 2, wherein the measurement of the desired DC characteristic is performed through at least one external test terminal for power supply other than the external test terminal for the test start signal among the plurality of external test terminals. A method for electrically testing integrated circuit memory device wafers. 4. A method for electrically testing a semiconductor integrated circuit memory device wafer comprising the following steps: (a) testing a large number of memory chip areas that have completed a wafer process for forming semiconductor integrated circuit memory devices on a semiconductor wafer; (b) For almost all of the chips to be tested among the large number of memory chips, the number of external pins of each chip is less than half the number of external pins of each of the chips after assembly. Step of bringing the external test terminal into contact; (c) Applying an AC test start signal from at least one test start signal external test terminal among the plurality of external test terminals brought into contact with each of the chips in the state of (b) above. (d) Automatically set each chip to an operating state corresponding to the test mode of a predetermined AC test based on the AC test start signal; AC in the above test mode
The process of performing measurements on a property. 5. The method of electrically testing a semiconductor integrated circuit memory device wafer according to claim 4, wherein said AC test is an AC function test. 6. The method of electrically testing a semiconductor integrated circuit memory device wafer according to claim 5, wherein generation of a test pattern corresponding to said test mode and determination of success or failure of read stored data are performed within each of said chips. 7. The method for electrically testing a semiconductor integrated circuit memory device wafer according to claim 6, wherein the test result is output to the outside of the wafer through at least one external test terminal among the plurality of external test terminals. . 8. A full wafer test method for testing a large number of memory chips formed on a semiconductor wafer almost simultaneously, characterized in that a DC test and an AC test are continuously executed on a large number of memory chips in a wafer state. Full wafer test method. 9. A full wafer testing method for a large number of memory chips in a wafer state as claimed in claim 8, wherein a test pattern necessary for said AC test is generated within each chip on said wafer.