JPS62143125A - Data read/write circuit for memory - Google Patents

Abstract

PURPOSE:To omit a selecting circuit and a latch circuit by using a counter circuit to be used at the reading of data from a buffer memory also at the writing of data. CONSTITUTION:To write data from a data I/O device 14 in a memory 16, a CPU 30 outputs a select signal from a SELECT terminal to invalidata a counter control circuit 38. Then, the CPU 30 outputs a signal '0' to an R/W' terminal to set up the memory 16 to a writing mode and outputs '0' to an I/O' terminal to set up a data I/0' device 14 to an output mode. The CPU 30 outputs the address value of a storing position of the memory 16 to be written to a bus 32 and sets up a LOAD terminal to '1', so that both counters 34, 36 enters the corresponding bits of the address value on the bus 43 into respective insides. Then, the CPU 30 stops the output to the bus 32 and sets up an OE2 terminal to '1' to output objective data from a data I/O device 14 to the bus 32. The memory 16 stores the data on the bus 32 in a specified storage position in response to the rise of the R/W' signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data read/write circuit for a buffer memory that temporarily stores data in a magnetic recording device.

[Conventional Techniques TFJ] In recent years, it has become common practice to convert still photographic images into video signals and then magnetically record them on floppy disks. Systems for making hard copies are being put into practical use. In response to this, it has been proposed to record binary signals on still video floppy disks, and standardization of the data recording format is also underway. According to that format,
Prior to recording, data signals recorded on a floppy disk are interleaved and an error correction code is added. Therefore, a buffer memory is required to temporarily store data signals for interleaving.

By the way, since addressing is complicated when writing data to this buffer memory, it is easier to control the address value using a CPU such as a microprocessor than to control the address value using hardware. On the other hand, when recording data on this magnetic recording medium, a buffer
Data must be read from memory at a uniform rate of 1.431818 MHz, and this high speed constant reading cannot be achieved with address control by the CPU. Therefore,
Conventionally, dedicated hardware has been provided for data reading, and the address control method has been switched between memory writing and reading.

FIG. 2 shows a block diagram of a conventional data read/write circuit. The cpuio is comprised of a microprocessor, such as a 780, and sends out address signals and data signals on the bus 12 in a time-division manner in order to reduce the number of input/output terminals. 13 is a control signal line.

A data input/output device 14 and a buffer memory 16 are connected to the bus 12, and a read terminal of the buffer memory 16 is connected to a magnetic recording device 18. Bus 1 like this
2 for data and address, when writing data to the buffer memory, the -H latch circuit 20 must hold the address sent in a time-division manner.

When dedicated hardware is used to read data from a buffer memory, the dedicated circuitry typically includes a counter circuit 22 that holds address values for the buffer memory;
a counter control circuit 24 that controls the next count value of the counter circuit 22 according to the held value of the counter circuit 22;
It consists of an initial value holding circuit 2G that holds an initial value set to . In order to switch between address control by this read-only hardware and address control by Cp U 10, a selection circuit 28 for selecting the output of the latch circuit 20 and the output of the counter circuit 22 is provided.

[Problems to be Solved by the Invention] Such a selection circuit can be constructed by combining gate circuits, but as a read/write circuit, the circuit inevitably becomes complicated. Furthermore, the latch circuit must take in only the address from time-divisionally transmitted addresses/data in a timely manner, which requires timing control.

Therefore, an object of the present invention is to provide a simpler data read/write circuit, specifically, a data read/write circuit that does not require a selection circuit or a latch circuit.

[Means for Solving the Problems] The data read/write circuit according to the present invention uses a counter circuit that is used when reading data from a buffer memory that temporarily stores data in a magnetic recording device to write data. It is also used when That is, this counter circuit is equipped with an O- upper terminal, and when writing data to the buffer memory, the CPU sends a load signal to both address counters,
Write is executed by loading both counters with address values indicating the write storage location.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an actual flow example. FIG. 1 shows a block diagram of one embodiment of the invention. The diagonally shaded lines indicate buses, and the numbers next to the diagonals indicate the number of lines or line numbers.

In FIG. 1, a CPU 30 sends data and address signals in a time-sharing manner onto a 16-bit bus 32, which is connected to a buffer memory 16 and a data input/output device 14. do.

The read line of buffer memory 16 connects to a magnetic recording device 18, such as a floppy disk drive. C.P.
Ll 30 is also a LOAD that outputs a LOAD signal.
Terminal, R/W terminal that outputs an R/W signal instructing writing and reading of buffer memory 16, buffer memory 1
an OE1 terminal that outputs an enable signal that enables data output from the data input/output device 14; It has an 0E2i child to output.

Bits 0-7 of data/address bus 32 connect to an 8-bit row address counter 34, and bits 8-13
is connected to column address counter 36.

This row address counter 34 is stored in the buffer memory 16.
The column address counter 36 defines the row address when each memory cell of is grasped in a matrix, and the column address counter 36 defines the column address. The output line of row address counter 34 corresponds to the 14 address lines of buffer memory 16.
The output line of the column address register 36 is connected to eight of the lines, e.g. 8 to 13).

38, both counters 34 and 36 depending on the count values of the row address counter 34 and the column address counter 36.
This is a counter control circuit that controls the operation of the counter.

Row address counter 34 includes a LOAD (load) terminal, a GE (clock enable) terminal, and a CLK (clock) terminal. When a load signal is input to the LOAD terminal, the counter 34 outputs the bit O on the bus 32.
Load the value ~7 internally.

Further, the counter 34 counts up in accordance with the clock signal at the CLK terminal when a logic high signal is input to the CE terminal. This LOAD terminal is the CPU's L
Connect to OAD terminal. The CEGa element is connected to the control signal output of the counter control circuit 38.

A clock signal from a clock circuit (not shown) is connected to the CLK terminal.

Column address counter 36 has a LOAD terminal, a CLR (clear) terminal, and a CLK (clock) terminal. The value of 13 is loaded internally.The counter 36 is cleared to 0 by a clear signal sent from the counter control circuit 38 to the CLR terminal, and counts up according to the clock signal of the CL K ON terminal.

The counter control circuit 38 is used exclusively when reading data from the memory 16 at a constant and high speed, and controls the count values of the column address counter 36 and the row address counter 34. Specifically, when it is detected that the count value of the column address counter 36 has reached a certain value (for example, 43), a clear signal is sent to the CLR terminal of the column address counter 36 to clear the count value to O. , At the same time, a clock enable signal is sent to the CE terminal of the row address counter 34 to read the row address by the clock signal.
The counter 34 is incremented by the number I~. In this manner, the matrix of memory cells of memory 16 is read out row by row at high speed. During this reading, the R/W@ child of the CP LJ 30 is "1" and the OEI terminal is also 1''.

The counter control circuit 38 is a 5ELEC of the CPU 30.
It is activated by a select signal from the T terminal.

When the CPU 30 reads data from the memory 16 using hardware, the CPU 30 outputs a select signal and also outputs an L
Output 0" from OAD terminal. LO of CPU 30
The AD terminal is connected to the LOAD terminals of both counters 34 and 36. Both counters 34 and 36 then capture the value of the corresponding bit position on bus 32 when a logic high load signal is input to the OAD terminal.

Next, the operation of the first illustrated circuit will be explained. First, a case in which data is input from the data input/output device 14 to the memory 16 will be described. In this write mode, CPU 30 disables counter control circuit 38 by issuing a logic high select signal from the 5ELECT terminal.

In addition, CP tJ 30 outputs an O'' signal to the R/W terminal to put the memory 1G into write mode, and outputs a signal 11 to the I 10 terminal.
011 to put the data input/output device 14 into output mode. However, at this point, the OE2 terminal of the CPU 30 is at 0°, so no data is output onto the bus 32. Further, the ○E1 terminal is also "0''.

The CPU 30 selects the memory 16 to which writing is to be performed.
Outputs the address value of the storage location of LOA onto the bus 32, and
Set the D terminal to “1”. Then, both counters are 34.36
takes in the corresponding bit of the address value of the bus 32 internally at the rising edge of the clock signal at the CLK terminal. This sets the address of the memory 16. Next, C.P.
The U 30 stops the output to the bus 32 and sets the OE2 terminal to "1", causing the data input/output device @14 to output the target data onto the bus 32.

The memory 16 stores the data on the bus 32 in a designated storage location in response to the rising edge ("O" → "1") of the R/W signal of the CPU 30.The memory 16 temporarily enters the read mode. However, since the input signal of the OE terminal is 0'',
No data is output to the outside. When the clock signal is too fast for this series of operations, the CPU
Select signal or LOA from 5ELECT terminal of 30
The signal from the D terminal can be used to divide the clock signal appropriately, or to switch to another slower clock signal.

When writing the next data, set the OE2 terminal to O'' to stop the output operation of the data input/output device 14, and then
The D terminal is set to "1°", new addresses are set in both counters 34 and 36, and the operation thereafter proceeds in the same manner as described above.

Next, a case in which data is read from the memory 16 will be described. The CP IJ 30 outputs values corresponding to the initial values of both counters 32 (for example, 0.0 for each) on the bus 32, and sets the LOAD terminal to 1''. The counter control circuit 38 is enabled by outputting a select signal from the OFF signal.The initial values are set in both counters 34 and 36 by the next ON signal, and at the same time, the CPU 30 sets the R/W terminal to 1''.
to put the memory 16 into read mode and set the OEI terminal to “1”.
Change it to ° to enable output. Also, the LOAD terminal is set to O''. In this read mode, the counter control circuit 3
8 is valid, the counter control circuit 38 uses the column address
A "0" signal is sent to the CLR terminal of the counter and the CE terminal of the row address counter 34. In response to the rise of the clock signal, the column address counter 36 counts up to a predetermined value. When the counter 36 reaches the predetermined value, , counter control circuit 38 controls C of column address counter 36.
A clear signal is sent to the LR terminal, and a clock enable signal is sent to the CE terminal of the row address counter 34. As a result, on the next rising edge of the clock signal, column address counter 36 is cleared and row address counter 34 counts up. In this way, data is sequentially read out from the memory 16 at high speed, and during this time the CPU
30 is not involved in address change.

In the above description, the counter 36 always defines a column address and the counter 34 always defines a row address. However, the present invention is not limited to this, and the counter 36 always defines a column address and the counter 34 always defines a row address.
The same applies to the case where the counter 6 is used for the row address and the counter 34 is used for the column address. The details of this switching use are as follows:
This is stated in the patent application dated February 11th.

[Effects of the Invention] As can be seen from the above description, according to the present invention, a write operation in which the data storage address must be changed arbitrarily to some extent is executed using the CPU, but it is performed at a constant and high speed. Read operations that must be read are performed by dedicated hardware. In the present invention, this is achieved by outputting two signals, a load signal and a select signal, from the CPU, and the number of additional circuit parts is extremely small. Furthermore, since the function of the latch circuit in the prior art is performed by the address counter, the latch circuit and the selection circuit for selecting between the counter circuit and the latch circuit are not required, and the overall circuit becomes simple.

[Brief explanation of drawings]

FIG. 1 is a configuration circuit diagram of one embodiment of the present invention.
The figure is a block circuit diagram of a conventional example. 10... CPU 12... Bus 13... Control signal line 14... Data input/output device 16... Buffer memory 18... Magnetic recording device 20... Latch circuit 22... Counter Circuit 24... Counter control circuit 26... Initial value holding circuit 28... Selection circuit 30... CPtJ 32... Data/address bus 34... Row address counter 36...
・Column address counter 38...Counter control circuit

Claims (4)

[Claims] (1) In a data processing system using a CPU that sends out address signals and data signals on a bus in a time-sharing manner,
When reading data from a buffer memory that temporarily stores data to an external recording device, an address counter circuit that specifies the read address of the memory and an address counter circuit that specifies the read address of the memory are used.
When writing data to the buffer memory using a counter control circuit that controls the value held by the counter circuit based on predetermined rules, the CPU loads the address counter circuit with an address value indicating the write memory location. A memory data read/write circuit characterized in that a memory data read/write circuit executes a write operation. (2) The address counter circuit includes first and second address counters, and in the case of data reading, the counter control circuit controls the first address when the first address counter changes to a predetermined value. - The memory data read/write circuit according to claim (1), which returns the counter to a predetermined value and changes the second address counter by a fixed amount. (3) When the first address counter counts up to a predetermined value, the counter control circuit clears the first address counter and clears the second address counter.
Claim No. 2 (
2) A data read/write circuit for the memory described in item 2). (4) A data read/write circuit for a memory according to claim (1), (2), or (3), in which the CPU disables the counter control circuit when writing data. .