JPS62182942A - Program debugger - Google Patents

Abstract

PURPOSE:To minimize intrusion of a trace memory into an actual operating memory area of a CPU by supplying the address of the trace memory from an up/down counter with the preset function. CONSTITUTION:When the trace address is read out, the CPU performs the read access to SL1 address, and SL1 and OC2 are set to the high level together. A signal RD goes to the low level, and the trace address written in a trace memory 1 is taken out onto a data bus. Each time the signal RD is inputted to an up/down counter 9 with the preset function, the counter 9 is decremented to designate the next address of the trace memory 1. When trace data is read out from the trace memory 1, the CPU performs the read access to SL2 address to set SL2 and OC4 to the high level together, and then, trace data written in the trace memory 1 is taken out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program debugging device.

[Conventional technology]

A conventional device of this type is shown in FIG. In the figure, 1 is a trace memory (in RA), 2 is an analog switch, and when DIR is “H” level, Y=A,
When DIR is at "L" level, Y=B. 3 and 4 are buffers, and when OCI and OC2 are at "H" level, A=B, and when OCI and QC2 are at "L" level, they become high impedance. Further, 5 is a counter.

Next, the operation will be explained. First, trace memory 1
When writing, the trace enable signal and the trace stop signal are at the low level, and the trace memory 1 performs chip select for each RD (read) signal and WR (write) signal from the CPU (not shown). The address, data, and command are written to the trace memory 1 via the buffer 3.The address of the trace memory 1 is stored in the counter until the trace stop signal reaches the it Hu level in order to input the RD double signal and the WR double signal. 5
is incremented by Next, when reading the trace memory 1, the trace enable signal and the trace stop signal become It H#l level, the address in the trace memory 1 is specified by the address bus, and the data is read 8 bits at a time via the buffer 4. put out.

6(a) to 6(k) are timing charts for writing to the trace memory 1, and FIGS. 7(a) to 7(k) are timing charts for reading.

[Problems to be Solved by the Invention] Since the conventional program debugging device is configured as described above, all operating processes executed by the CPU are stored in the trace memory until the trace signal reaches the glHIt level. The amount corresponding to the capacity will be stored in the trace memory. Therefore, there is a problem in that when the capacity of the trace memory is increased, the memory area used by the CPU is correspondingly reduced.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a program debugging device that can increase the trace memory capacity to infinity and minimize the influence on the memory area of the CPU. .

[Means for solving problems]

The program debugging device according to the present invention chip-selects the trace memory according to the RD double signal and the WR double signal, writes an address and a command to the trace memory, and updates the address of the trace memory with the RD double signal until a trace stop signal is input. The counter is incremented by the WR multiplication signal, and when reading the contents of the trace memory, an arbitrary address value is set from the stopped address value or from the CPU, and then the counter is decremented by the read enable signal and the RD multiplication signal. The trace contents are read out sequentially at the same address.

[Effect]

In the trace memory according to the present invention, a counter is incremented by an up/down counter at the time of writing. Further, at the time of reading, the counter is decremented and the address of the trace memory is appropriately indicated by the counter, thereby writing to and reading from the trace memory is performed, and tracing is performed regardless of the memory area of the CPU.

In FIG. 1, the same parts as in FIG. 5 are designated by the same reference numerals. In FIG. It has a memory 1c for tracing.

Further, 10 is a program memory of the system.

Since the tracing memory 1 of the present invention shown in FIG. 1 is provided in a space separate from the program memory 10 of the system,
The area of the program memory 10 of the system is minimally occupied, and the capacity of the trace memory 1 can be increased without limit. When reading the trace memory 1 from the program memory area of the system, it is sufficient to access one arbitrary address provided in advance on the system program.

Address 5L=XXXX in FIG. 1 indicates an arbitrary address. Further, the capacity of this address may be set from one to an arbitrary value depending on the size of the program debugging device.

In particular, if the capacity cannot be obtained on the memory map, it may be provided on the IO boat.

Next, the operation of this invention will be explained. First, in FIG. 2, when writing to the trace memory 1, the up/down counter 9 with a preset function is cleared to zero by a reset ID number d.

The trace stop signal is then set to R from the CPU (not shown) with the trace enable signal as It L II.
The trace memory 1 is chip-selected by the D times signal and the WR times signal, and the address and data are written into the trace memory 1 via buffers 3 and 6. Also, the address of trace memory 1 is 1-race stop signal is “H1”
It is incremented by the up/down counter 9 every time the RD multiplied signal and the WR multiplied signal are input until it becomes 1.

When reading the trace memory 1, the trace enable signal becomes "H". First, the ID3 signal may be set to "H" and the final value of the preset up/down counter 9 may be read out via the buffer 8 by a CPU (not shown). Also, when reading the trace memory 1 from the final value of the up/down counter 9, the IO3 signal is set to L''.
shall be.

Next, when reading the trace address, the CPU
A read access is made to address 1, SLI is set to "ttH", and OC2 is set to "H".

Subsequently, the RD double signal 11L becomes 11, and the trace address written in the trace memory 1 is taken out onto the data bus. Then, each time the RD times signal enters the up/down counter 9 with a preset function, it is decremented by 1.
Specify the address of the next trace memory 1. Similarly, when reading the trace data from the trace memory 1, the CPU makes read access to the SL2 address, sets Sb2 to "H+t", sets OC4 to tl HII, and trace data written in the trace memory 1. can be taken out.

Further, when reading the contents of the trace memory 1 from an arbitrary address, an arbitrary address value is set on the data bus, the IO3 signal is set to 11 L j+, and the address value is set in the up/down counter 9 with a preset function.

In the following, the trace address and trace data in the trace memory 1 are read from an arbitrary address via the buffer 4 or the buffer 7 by operations similar to the above trace address reading or trace data reading.

3(a) to 3(p) are timing charts for writing to the trace memory 1, and FIGS. 4(a) to 4(p) are timing charts for reading trace addresses from the trace memory 1.

〔Effect of the invention〕

As described above, according to the present invention, since the circuit is configured so that the address of the trace memory is supplied by the up/down counter with the preset function, the trace memory is
This has the effect of minimizing the invasion of the actual working memory area of u (not shown).

[Brief explanation of drawings]

FIG. 1 is a memory diagram showing the principle of the present invention, FIG. 2 is a block circuit diagram of a trace memory circuit of a program debugging device according to an embodiment of the present invention, FIG. 3 is a timing chart during tracing, and FIG. 5 is a block circuit diagram of a trace memory circuit of a conventional program debugging device; FIG. 6 is a timing chart when writing trace contents; FIG. 7 is a timing chart when reading trace contents.
The figure is a timing chart when reading the trace memory. In the figure, 1 is a trace memory, 3, 4° 6.7.
8 is a buffer, 9 is an up/down counter, and 10 is a system program. Patent Applicant: Mitsubishi Electric Co., Ltd. Figure 1 Figure 1 Method for Nidrace Figure 2 Figure 3 Figure 4 Figure 5

Claims (3)

[Claims] (1) Chip select the trace memory for each read signal and write signal, write address data and commands to the trace memory, and write the address of the trace memory every time the read signal and write signal are input until the trace stop signal is input. What is claimed is: 1. A program debugging device comprising a counter that increments the trace contents by a decrement counter, wherein an address of the trace memory is selected by a decrement counter when reading the trace contents. (2) The counter for selecting the address of the trace memory is an up-down counter with a preset function, and the content of the trace memory is read by the up-down counter. A program debugging device according to scope 1. (3) The program debugging device according to claim 1, wherein the count value of the address instruction counter of the trace memory can be read.