JPS58123145A - State history storage device - Google Patents

Abstract

PURPOSE:To use a storage region with high efficiency, by selecting and writing the 2nd state information to a storage device as long as the 1st state information has no change during the repetitive collection of the state information. CONSTITUTION:The old 1st state information set to a buffer register 3 is compared with the new 1st state information which is sent out. Then the logic value is set at 0 for the output information of a comparator 4 if no coincidence is obtained from the comparison. Thus a selector 2 selects the new 1st state information and adds the output information of the comparator 4 as an index to write them in a designated address of a storage device 5. While if the coincidence is obtained from the above-mentioned comparison, the logic value is set at 0 for the output information of the comparator 4. Thus the selector 2 selects the 2nd state information and adds the output information of the comparator 4 as an index to write them in a designated address of the device 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage device inside an information processing device, and in particular, it divides state information into first and second state information, and when there is a change in the first state information, a new one is stored. The present invention relates to a shape storage device configured to update and store first state information, but to store second state information only when there is no change in the first state information.

Conventionally, information processing equipment detects an abnormality during operation),
If the operation stops due to a failure, one way to investigate the cause of the abnormality or failure is to store information about the internal state of the device up to the time the abnormality or failure was detected as historical information, A method is adopted in which the cause of an abnormality or failure is determined by changing information. In this method, the storage device for storing state information is used as a tracing storage device. Therefore, this memory device WIK
Since the content to be written is specified in advance, if the new storage content is the same as the old storage content, the same content is repeatedly written to the storage device. Therefore, there was a drawback that the storage area was not used effectively.

An object of the present invention is to divide state information inside an information processing device into @1 state information and second state information, and use the second state information for tracing only when there is no change in the first state information. It is an object of the present invention to provide a state history storage device configured to store data in a storage device, thereby making it possible to effectively utilize the storage area of a tracing storage device.

To achieve the above object, the state history storage device M according to the invention includes a controller, a selector, a buffer register, a comparator, a memory, an address register, and an adder.

The controller divides the state information inside the information processing device into first state information and second state information, and sends these state information to the selector.

The selector operates in response to a select signal from the comparator, selects the first state information or the Fi@2 state information, and sends the selected state information to the storage device.

A buffer register is used with the comparator to hold first state information.

The comparator is a device for detecting changes in the first state information and compares the new first state information with the old first state information held in the buffer register.

The storage device has a role as a tracing storage device, and stores first or second status information that is generated sequentially at sequentially designated addresses.

Address registers and adders are used together to address storage devices.

The controller sends first state information to the selector, buffer register, and comparator. When new first state information is set in the buffer register, the old first state information that was previously set is added to the comparator. A comparator compares this old first state information with new first state information sent from the controller. If both first state information are different, the selector selects the first state information by the select signal obtained from the output terminal of the comparator.

The first state information selected by the selector is integrated with the output information of the comparator, is identified as the first state information, and is stored in the storage device in a rounded form. If the new first state information and the old first state information match, the select signal obtained from the output terminal of the comparator selects
The selector selects the second state information being sent from the controller.

The 20th state information selected by the selector is integrated with the output information of the comparator, and is stored in the storage device after being made clear that it is the second state information. This makes it possible to effectively utilize the storage area of the storage device provided for tracing! 2). This storage device is used together with an address register and an adder, that is, the address register and the adder are combined to designate the address of the write destination in the storage device.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a state history storage device according to the present invention. In the figure, a controller 1 generates first and second state information.

The first status information generated by the controller 1 is transmitted to the selector 2. Buffer register 3° and comparator 4
Sent to the 0 input terminal. On the other hand, the second state information of the controller 1 is sent to the other input terminal of the selector 2 via the signal line 22.

The first state information being applied via the signal line 21 is written into the output register 3 in response to a write timing signal sent from the controller 1 via the signal @26. As information is written to the buffer register 3, the old first state information held in the buffer register 3 is read out to the signal line 23. The old first state information sent on signal 1123 is applied to the comparator 40 input terminal. On the other hand, the new first status information being sent on the signal line 21 is applied to another input terminal of the comparator 4. Comparator 4Fi compares these first state information. If these pieces of information match, the logical value of the output information of the comparator 4 becomes 1, and if they do not match, the logic value of the output information of the comparator 4 becomes 1.
The logical value of the output information becomes O. The output information of comparator 4 is sent out via signal 1124 and applied to the select signal terminal of selector 2 and the index terminal of storage device 5. The index terminal is added to the storage device S and is provided to distinguish whether the 9 information is the first state information or the tft is the second state information. Signal line 24 from comparator 4
If the logical value of the select signal sent to the selector 2 via the controller 1 is O, the controller 1 is also sent via the signal line 21, and the status information of the Odate 1 is selected by the selector 2 and sent to the signal line 2s.
sent to. If the logical value of the 9 select signal sent from the comparator 4 to the selector 2 via the signal line 24 is 1,
The second status information sent from the controller 1 via the signal 1s22 is the selector? is selected and sent to the signal line 2s. The information sent to signal 11125 is added to storage 5 for tracing. Since the write timing signal is applied from the controller 1 to the storage device 5 via the signal 1126, the information sent to the signal 1125 and the signal @2
4 is written to the storage device S according to this write timing. The information being sent to the signal line 25 is selected by the selector 2 and is output from the selector 2, so it is first or second status information. Additionally, the information being sent to the signal line 24 is the information output from the comparator 4. When the first status information is selected, the logical values of this information are 4 and 1;
The logical value is 0 when the second state information is selected. Therefore, this information is stored in the first state information in the storage device 5.
It is used as index information indicating whether the second state information is being sent to the storage device 5 or whether the second status information is being sent to the storage device 5. The address register 6 specifies the address of the storage device 5, and the address given by the contents of the address register 6 represents the address to which information is written in accordance with the write timing signal on the signal line 26.

The output of the address register 6 becomes the address information of the storage device 5 and is also added to the addition 1iF7 via the signal line 211. The output information of the adder T is applied again to the address register 6 via the signal line 2T. The adder 1 adds a certain value, for example +1, to the contents of the address register 6, and the adder TO operation allows the address register @ to designate the next write address to the storage device S.

The above-described operations are repeated every time a write timing signal is sent from the controller 1, so that a series of status information is written into the storage device 5. Further, as already explained, the first status information sent from the controller 1 via the signal line 21 is added to the buffer register 3. Therefore, this first state information is set in the buffer register 3 in response to the write timing signal applied to the buffer register 3 via the signal ls2@. Therefore, the contents of the buffer register 3 are always updated at each write timing, and the latest first state information is always held in the buffer register 3.

The outline of the operation explained above will be summarized below.

The old first status information set in the buffer register 3 last time and the new first status information sent this time are compared, and if they do not match, the logical value of the output information of the comparator 4 is Becomes Fio.

Then, the selector 2 selects new first state information, adds the output information of the comparator 4 as an index, and stores it in the storage device 5.
In this case, the write destination address is given by the address register 6. on the other hand,
When the information to be compared matches, the logical value of the output information of the comparator 4 becomes O. Therefore, the selector 2 selects the second state information, adds the output information of the comparator 4 as an index, and writes both to the specified address of the storage device 5. In this case, the write destination address is also in the address register. It is given by 6.

As explained above, the 11th or 2nd state information is stored in the trace storage device, but if the 11th or 2nd state information is not changed during the repeated state information collection process, Only the second status information is selected and written to the storage device. Therefore, the state history storage device configured according to the present invention has the effect and advantage that the storage area of the storage device can be used efficiently and effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a state history storage device according to the present invention. 1...Controller 2@...Selector 3...Buffer register 4...Comparator 5...Storage device 6...Address register T...Adder 21 to 21--Signal line Figure j

Claims (1)

[Claims] In an information processing device that sequentially stores internal state information and uses the state information to investigate causes of abnormalities or failures during operation, the state information is divided into first state information and second state information. a controller to send out, a selector to select either the first state information or the second state information, a buffer register to hold the first state information, and an old state information previously held in the buffer register. a comparator that compares the first state information with the new first state information sent out this time; a storage device that separately stores the first state information or the second state information as trace information;
an address register and an adder for use with the storage device; the selector sends the second status information to the storage device when the output of the comparator indicates a match; A state history storage device configured to send the first state information from the selector to the storage device when the information indicates a mismatch, and to distinguish and store the first state information in the storage device.