JPH03231539A - Shared memory type packet switch - Google Patents

Abstract

PURPOSE:To save the quantity of hardware by providing an associative storage memory circuit having a collation function of a symbol string. CONSTITUTION:An idle area of a memory circuit 14 is retrieved by detecting output command information not outputted to output lines 9-11, that is, output command information not designating an outgoing line. Thus, designated retrieval information is sent to an associative storage memory circuit 15 and whether or not the designation of an outgoing line is entirely implemented is compared and collated and as a result, when the coincidence is detected, that is, the designation of all outgoing lines is not implemented, the presence of an idle area in the memory circuit 14 is detected. When the coincidence is not detected, it is discriminated that no idle area exists in the memory circuit 14 and the inputted packet data is aborted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet switch for a packet switch that performs switching processing in units of packets, and particularly relates to a high-speed shared memory type packet switch that performs packet switching using only hardware circuits. It is something.

[Prior Art] Conventionally, an ordinary memory is used as a shared memory circuit for writing and storing input packets. When writing a packet to this memory circuit, write to a predetermined area in this memory circuit according to the destination of this write packet, and when reading a packet from the memory circuit, output the packet. The packet is being read from the destination area.

Then, in order to write and read packets to and from the memory circuit, a write pointer address register indicating the address of the memory circuit that has already been written and is occupied by a packet has been written, and a write pointer address register that indicates the address of the memory circuit that has already been written and is now free. A number of read pointer address registers are provided for each output line.

When writing a packet to a memory circuit, the address of the next memory circuit to be written is determined from the value of the write pointer address register, and the write operation is performed based on this. When the write is completed, the value of this pointer address register is increased by +1, That is, increment.

Also, when reading a packet, the next address to be read is determined from the value of the read pointer address register, and the read operation is performed based on this. When the read is completed, the value of this pointer address register is +
Do 1. In this way, the packets stored in the memory circuit are output to the designated destination.

Also, if you want to output one packet to multiple destinations,
Copies of packets corresponding to the number of destinations are created in advance before writing to the memory circuit, and processing is performed to write these duplicated packets to the memory circuit.

[Problem to be Solved by the Invention 1] The conventional packet switch described above writes to an area according to the destination of the packet in a predetermined memory circuit, so a large number of packets destined for a specific destination are input. In this case, a large number of packets will be concentrated in the memory area of the corresponding destination, and in this case, this packet cannot be written to the memory area of other destinations.
There is a problem in that input packets are likely to be lost, and therefore a wide memory area must be secured for each outgoing line, and a large-capacity memory circuit is therefore required. Furthermore, when transmitting the same packet to multiple destinations, a separate circuit for duplicating the packet is required, resulting in an increase in the amount of hardware.

[Means for Solving the Problems] In order to solve such problems, the shared memory type packet switch according to the present invention has an area for storing output instruction information in which one bit is assigned to each destination outgoing line. One symbol string is provided for each address. When a specific symbol string is given, it is compared with the output instruction information and the comparison result is output as a match or mismatch signal. If it matches the output instruction information, this matched output instruction information is output. It is equipped with an associative memory circuit that outputs existing addresses and a memory circuit that stores packets.

[Operation] When writing a packet, if the output instruction information does not indicate output to all outgoing lines, the packet is written to the area of the memory circuit at the same address as the address corresponding to the destination of the packet. At the same time, the value of the output instruction information corresponding to this address is rewritten to the output instruction value,
In addition, when reading a packet, only the output instruction information area for the outgoing line corresponding to the time slot position of the output time division bus is compared with the value instructed to be output, and the value is checked from the area of the memory circuit at the matching address. At the same time that the packet is read and output to the specified outgoing line, the output instruction information value corresponding to this address is rewritten to a value that does not instruct output, and the input packet has multiple destination information. In this case, the same packet is duplicated and sent to multiple outgoing lines.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a packet switch to which a shared memory type packet switch of the present invention is applied. In the figure, 1 to 3 are input lines, 4 is a multiplex circuit, and 5 is an input line.
is an input time division bus, 6 is a shared memory circuit, 7 is an output time division bus, 8 is a separation circuit, 9 to 11 are output lines, 12 is a write control circuit, 13 is a read control circuit, 14 is a memory circuit, 15 is an associative memory circuit.

Then, packet data having various destinations at the beginning arrives at the input lines 1 to 3, and these packet data are time-division multiplexed by the multiplexing circuit 4. This multiplexing process transfers input packet data from input line 1 to
Since the number of time slots is equal to the number of input lines, even if packet data arrives at all input lines 1 to 3 at the same time, It can be multiplexed.

The packet data multiplexed in this way is transferred to the shared memory circuit 6 that temporarily stores the packet data via the input time division busler, and is written to the memory circuit 14 in this shared memory circuit 6 by the write control circuit 12. .

At this time, at the same time as writing this packet data, the write control circuit 12 determines to which output line this packet data should be sent based on the destination information in the packet data, and sends this determined output instruction information. Write to the associative memory circuit 15, where the associative memory circuit 15 is composed of a sequential circuit and a memory,
At least one or more finite number of symbol strings can be written and registered, and the symbol string input sequentially from the outside in symbol units is compared with all the registered symbol strings at the same time, and one of the registered symbol strings can be registered. If there is a match with three or more, at least one registered address of the registered symbol string that matches the minus number display signal is output.

On the other hand, the readout control circuit 13 controls the associative memory circuit 1
The packet data is read out from the memory circuit 14 based on the address obtained from the output instruction information. 8, where it is separated and sent to a desired output line.

Next, FIG. 2 is a block diagram of the shared memory circuit 6. As shown in FIG. Note that (a) of the same figure shows the configuration of the memory circuit 1-4,
Further, FIG. 1B shows the configuration of the associative memory circuit 15. As shown in FIG. In FIG. 2, 20 is a packet data area where packets are stored, 21 is an output instruction information area where output instruction information is stored, and 22 is an output instruction bit corresponding to an outgoing line forming the output instruction information.

Next, the operation of the present invention will be explained in detail based on FIGS. 1 and 2.

When packet data to be output from the input line 1 to the output line 9.10 arrives, the destination information at the beginning of the packet data is read to determine whether it should be sent to the output line 9.10. This input packet data is
The multiplex circuit 4 multiplexes the data with packet data from other input lines and sends it to the shared memory circuit 6. Here, the write control circuit 12 identifies whether or not packet data exists within the time slot from the multiplex circuit 4 by detecting a control flag (not shown) on the time slot. If packet data exists in the memory circuit 14, it is first searched whether there is a free area in the memory circuit 14 to write this packet data.

The empty area of the memory circuit 14 can be searched by detecting output instruction information that does not have a value to be output to an output line, that is, output instruction information that does not specify an outgoing line.

Therefore, the search information for specifying the outgoing lines is sent to the associative memory circuit 15 to compare and check whether all outgoing lines have been specified. If no line is specified, it means that there is an empty area within the memory circuit 14. If no match is detected, it means that there is no free space in the memory circuit 14, and the input packet data is discarded.

However, even if the packet data input at the same time is discarded, as will be described later, if the packet data is read from the memory circuit 14, an empty area will be created in the memory circuit 14, so the packet data will be discarded. Can be rewritten.

In this way, the input packet data using the address based on the destination information is written to the corresponding free area of the memory circuit 14, that is, the area corresponding to the output line 9.10 in this case, and at the same time, the input packet data is written using the address based on the destination information of the packet data. The output line to which the packet data should be output is determined, and this is used as output instruction information in the content addressable memory circuit 1.
Write to the corresponding address in 5.

Here, in this output instruction information, as shown in FIG. 2, each bit in this output instruction information, that is, the output instruction bit 22 corresponding to the outgoing line, indicates which output line the packet data is to be sent to, In the case of packet data sent to multiple output lines, the video signal at the position corresponding to multiple output lines is
By setting 7 to the output instruction value, the same packet data can be sent to multiple output lines.

In this case, the input packet data is output line 9.10.
Therefore, the value of the bit position corresponding to the output line 9.degree. 10 is written to the content addressable memory circuit 15 with the output instruction set and the other bits set as output non-indication. In this way, by writing the output instruction value into the output instruction information, the area of the memory circuit 14 indicated by the corresponding address becomes occupied.

Furthermore, time slots corresponding to the output lines are allocated to the output time division bus 7, and time slots for each output line appear in sequence, and when this goes around, a time slot for the same line appears again. Readout control circuit 13
searches and reads out packet data to be sent to the corresponding output line from the memory circuit 14 in accordance with this time slot. As a result, the packet data is sent to the intended output line.

Assuming that the time slot position corresponds to output line 9, the read control circuit 13 instructs the associative memory circuit 15 to output the bit of the output instruction information at the position corresponding to output line 9. Compare and check whether the instructions are met or not. Note that at this time, the associative memory circuit 15 does not compare and verify the values of the bits at positions corresponding to other output lines. Then, as a result of comparison and verification by the associative memory circuit 15, if they match, the packet data in the memory circuit 14 is read out using the matched address and placed on this time slot. At the same time, the bit corresponding to the output line 9 in the output instruction information at the same address in the content addressable memory circuit 15 is rewritten from output instruction to output no instruction.

Next, when the time slot position reaches a value corresponding to the output line 10, the readout control circuit 13 performs the same operation as described above. Note that even if the packet data has already been read out to the output line 9 at this time, the bit at the position corresponding to the output line 10 in the output instruction information is designated as output, so the data from the readout control circuit 13 is According to verification instructions -
- A match is obtained, and as a result, the same packet data is sent to the output line 10. After that, the bit corresponding to the output line 10 is similarly rewritten to output unspecified.

In this way, even if the input packet data is to be sent to multiple destinations, if the read operation is repeated several times, the same packet data will be read to all destinations, and the corresponding All bits of the output instruction information to be output are rewritten to output unspecified. As a result, the area of the memory circuit 14 indicated by the corresponding address becomes empty, and the address of this empty area can be obtained by checking the empty status of the memory circuit 14 at the time of writing, and other packets input again The data will be stored.

As explained above, by providing the content addressable memory circuit 15 having a symbol string matching function in the shared memory circuit 6, there is no need to divide the memory area for storing packet data for each destination, and This eliminates the need for a replication circuit when writing packet data destined for a destination into a memory area, and has the effect of significantly reducing the amount of hardware required.

[Effects of the Invention] As explained above, the shared memory type packet switch of the present invention is provided with an associative memory circuit having a symbol string collation function, so that the memory area of the memory circuit for storing packet data can be allocated for each destination. There is no need to divide packet data into multiple destinations, and no duplication circuit is required when writing packet data to multiple destinations into a memory area, resulting in a significant reduction in the amount of hardware required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a packet switch to which the shared memory type packet switch of the present invention is applied, and FIG.
The figure is a configuration diagram of a shared memory. 1-3...Input line, 4...Multiple circuit, 5-...
・-Human power time division bus, 6... Shared memory circuit, 7.
... Output time division bus, 8-... Separation circuit, 9 to 11
...Output line, 12--...Write control circuit, 1
3...-1 reading control circuit, 14... memory circuit, 15... associative memory memory circuit.

Claims (1)

[Scope of Claims] A multiplex circuit that time-divisions and multiplexes packets on one bus, in which at least destination information indicating the transfer destination of this information is added to the head part of information arriving from a plurality of input lines. , an input time division bus that transfers the output information from this multiplex circuit, and packets on this input time division bus are sequentially written into free areas in memory, and the additional information in the written packets is referenced to correspond to the destination. If the same packet is sent to multiple destinations, read this packet multiple times depending on the destination, output the same packet to each destination, and read and output the packet to all destinations. A shared memory circuit that frees the area where the packet was stored after performing this process, and a shared memory circuit that sequentially reads packet information corresponding to the destination from this shared memory circuit and allocates it to the time slot position of the line corresponding to the packet destination. an output time division bus that multiplexes and transfers different packets to each destination by transmitting the same, and a separation circuit that outputs the packets on the output time division bus to an outgoing line corresponding to the time slot position. In a shared memory type packet switch, an area is provided in the shared memory circuit and stores output instruction information in which one bit is assigned to each destination outgoing line.
One symbol string is provided for each address, and when a specific symbol string is given, it is compared with the output instruction information and the comparison result is output as a match or mismatch signal, and if it matches the output instruction information, this matched output instruction information a content addressable memory circuit that outputs an address where the shared memory circuit exists, and a memory circuit that is provided in the shared memory circuit and stores a packet, and when writing a packet, the output instruction information is an output instruction for all outgoing lines. If not, write the packet to the area of the memory circuit at the same address as the address corresponding to the destination of the packet, at the same time rewrite the value of the output instruction information corresponding to this address to the value of the output instruction, and read the packet. In this case, the output instruction information area for the outgoing line corresponding to the time slot position of the output time division bus is checked against the output instruction value, and the packet is read from the memory circuit area of the matching address. At the same time as outputting to the specified outgoing line, the value of the output instruction information corresponding to this address is rewritten to a value that does not instruct output, and if the input packet has multiple destination information, the same packet is duplicated. A shared memory type packet switch characterized by being able to send data to multiple outgoing lines and output to multiple outgoing lines.