JPH0834481B2 - Packet switch - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a packet switch, and more particularly to a packet switch having a high-speed packet switch that realizes a switching function only by a hardware circuit.

[Conventional technology]

A conventional packet switch uses an ordinary general memory as a shared memory circuit for writing and accumulating an input packet, and a memory corresponding to a predetermined destination on the memory according to the destination of the write packet at the time of writing to the memory. At the time of writing and reading in the area, the reading operation was performed to the memory area corresponding to the destination that outputs the packet.

Furthermore, in the memory area corresponding to a predetermined destination on the memory, a write pointer address register that indicates an address that has been blocked by writing a packet, and an empty area by reading already. The read pointer address register for indicating the address that has been set is provided for each output line, and when writing packet information to the shared memory circuit, the write pointer address register is used to find the next writable memory address and the write operation is performed. Then, the write pointer address register is incremented by one. At the time of reading, the address to be read next is obtained from the read pointer address register, the read operation is performed, and then the process of incrementing the read pointer address register by 1 is performed.

[Problems to be Solved by the Invention]

Since the conventional packet switch described above writes in a memory area corresponding to a predetermined destination on the memory according to the destination of the packet, it is applicable when only a large amount of packet information for a specific destination occurs. Since the memory area corresponding to the destination is filled with the written packet information and it is not possible to write even if there is a space in the memory area corresponding to the other destination, the packet information generated after that tends to be lost. However, in order to avoid this, it is necessary to make the memory area corresponding to each destination sufficiently wide, and a very large capacity memory is required for the shared memory circuit, so there is a problem that it is economically burdensome. It was

[Means for solving the problem]

The packet switch of the present invention comprises a multiplexing circuit for time-division multiplexing packets input from a plurality of input lines on one bus, an input time division bus for transferring output information from the multiplexing circuit, and the input circuit. Packets on the time-division bus are written and written one after another to the empty area of the memory. The packets are output corresponding to the destination by referring to the additional information in this packet. After the output, the area where the read packet is stored is stored. And a packet having different destinations by putting packet information sequentially read from the shared memory circuit corresponding to the destination into the time slot position of the output line corresponding to the destination of this packet. An output time division bus that multiplexes and transfers
In a packet switch having a separation circuit having a function of outputting a packet on the output time division bus from the time slot position to a corresponding output line, the shared memory circuit is provided with a specific symbol string. When the result of the comparison is output as a match or mismatch signal and at the same time a match is found, the address on the shared memory circuit where the matched packet information exists is stored in the packet storage address. It is configured by an associative storage memory circuit having a symbol string collating function of outputting as, and 1 bit in the packet storage address in the shared memory circuit is allocated to a display bit indicating empty space, Packet storage address by comparing and collating all bits with empty value Detects a vacant address, writes the input packet including the destination information, and rewrites the display bit to the closed state, and outputs it to the area that stores the destination information in the packet when reading the packet. Performs a comparison and collation operation with the value of the destination to detect the address where the packet of the same destination as the output destination exists, and by reading the information of this address, the packet output to the output line corresponding to the output destination is sequentially performed. After the output of the packet, the value of the display bit is rewritten to an empty state to enable the writing operation of the packet to be input next, and the shared memory circuit is configured so that only the additional information including the destination information in the packet information is included. The packet writable address is known by comparing and collating the display bit that indicates that the space is full Associative memory having a function of being able to know the storage address of a packet of a specific destination by comparison and collation with information, and a memory circuit having a function of specially writing and storing communication information excluding additional information in the packet information. And an additional information including a destination information of the packet information, which is commonly used when writing the packet information to the associative memory circuit and the memory circuit When writing and reading the communication information and reading the packet information from the associative memory circuit and the memory circuit using the address obtained from the collation operation of the associative memory circuit at the time of reading, the packet information corresponding to the destination is obtained. May be configured to be sequentially output.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of the first embodiment of the present invention.

Ingress line where packets with different destinations enter
The packets on 1, 2, and 3 are time-division multiplexed by the multiplexing circuit 4 on the packets of all lines. In multiplexing, the time slot position to put the input packet is decided corresponding to the input lines 1, 2 and 3, and since the time slot is provided for the number of input lines, the packets from all the input lines 1, 2 and 3 can be sent simultaneously. Even if there is an input, it can be multiplexed. The multiplexed packet is transferred to the shared memory circuit 6 that temporarily stores the packet by the input time division bus 5, and is written in the associative memory circuit 14 in the shared memory circuit 6. Here, the associative memory circuit 14 is composed of a sequential circuit and a memory,
It is possible to write and register at least one finite number of symbol strings, and simultaneously compare and collate the symbol strings that are sequentially input from the outside on a symbol-by-symbol basis with all the registered symbol strings that have been registered. When a match is found with any one or more of the symbol strings, it has a function of outputting the match display signal and the registered address of the registered symbol string. When a packet arrives from the input time division bus 5, the write control circuit 12 instructs the associative storage memory circuit 14 to perform a collation operation in an empty state, and when an empty address is obtained, it arrives at this address. At the same time as writing the packet, the empty block display bit in the associative memory circuit 14 is blocked and displayed. The output time division bus 7 is for transferring the packet read from the shared memory circuit 6 to the output lines 9, 10, 11 and has a time slot corresponding to the output lines 9, 10, 11 Packet placed in the time slot of the output line 9,1 corresponding to the time slot position
It is output to 0 and 11. The read control circuit 13 is for controlling the reading of packets from the associative memory circuit 14, and selectively outputs the packets to the output line corresponding to the time slot on the output time division bus 7. The circuit 14 performs the comparison and collation operation based on the destination information. At this time, if there is a packet to be output on the shared memory circuit 6, the packet is read out based on the storage address of the packet obtained by the comparison and collation operation, and then the empty block display bit on the associative memory circuit 14 is displayed. Is rewritten from the closed display to the empty display.

FIG. 2 is a configuration diagram showing a basic configuration of the packet on the memory.

A packet is composed of communication information in which information to be communicated is divided into blocks of a certain length, and destination information indicating the destination of this packet. When the length of the communication information is long, it is decomposed into a plurality of packets having the same destination information.

FIG. 3 is a configuration diagram showing how packets are stored in the associative memory 14.

A packet having the configuration shown in FIG.
They are stored one by one, and have an empty block display bit added to the head position of each.

Next, the operation will be described with reference to FIG. 1, FIG. 2, and FIG. First, in FIG. 1, the packet having the configuration shown in FIG. 2 which is input from the input lines 1, 2, and 3 includes the destination information at the beginning. Assume that the destination information is the number corresponding to the output lines 9, 10, 11. It is assumed that the packet having the value of the destination “1” is a packet to be output to the output line 9. Similarly, the value of the destination "2" is the output line 10 and the value of "3" is the output packet to the output line 11. These packets are aperiodically multiplexed and input to each of the input lines 1, 2, and 3. Packets from all the input lines 1, 2, 3 are time-division multiplexed by the multiplex line 5 and transferred to the associative memory circuit 14. The associative memory circuit 14 has the configuration shown in FIG.
When 12 performs a check operation of the empty state for the empty block indication bit, if there is an empty address in the associative memory circuit 14, a match is made and the matched address is output. It If no vacant match is found, it means that the associative storage memory circuit 14 has already overflowed, so writing of the packet becomes impossible and the input packet is discarded. When the packet is discarded for a certain period of time, the packet is read from the associative storage memory circuit, so that an empty area is created and a match can be obtained by checking the empty space, and the write operation can be performed.
The write control circuit 12 writes the packet by using the vacant address thus obtained. At this time, the empty block indication bit is written as a block value at the same time as the packet.

The output time-division bus 7 has time slots corresponding to the output lines 9, 10 and 11, and the time slots to the output lines 9, 10 and 11 sequentially appear, and the time to the same line is again displayed in one cycle. Slots appear. The read control circuit 13 operates so as to read the packet to the corresponding output line 9, 10, 11 in accordance with this time slot. Now, it is assumed that the time slot to the output line 9 has started. The read control circuit 13 performs a collating operation with respect to the destination information on the associative storage memory 14 and the empty block display. The condition for matching is an address that has a value of the destination “1” corresponding to the output line 9 and is closed. If no match is found in the matching operation, there is no packet to be output, and no read is performed.
If a match is found, output line 9 is placed on the matched address.
This means that there is a packet to be sent to, so that this packet is read, and then the empty block indicator bit is rewritten from the block value to the value in the empty state so that the packet can be written to that address. Similarly, when a time slot corresponding to the output line 10 next appears on the output time division bus 7, a matching operation is performed between the destination "2" and the blocked state, and the packet reading operation is performed.

FIG. 4 shows the shared memory circuit 6 of the packet switch shown in FIG. 1 as a general memory circuit 15 and an associative memory circuit 16.
It is a block diagram of the 2nd Example which it was set as the structure which consists of. FIG. 5 is a block diagram showing how packets are stored inside the shared memory circuit. As shown in FIG. 5, since the destination information and the empty block bit are stored in the associative storage memory circuit 16, it is possible to perform the empty matching operation and the matching operation corresponding to the destination as in the packet switch shown in FIG. It is possible. Since the communication information does not participate in the matching operation, it is stored in the normal memory circuit 15. The address for storing information is stored in the associative memory circuit 16 and the memory circuit 15, and the information for the same packet is stored in the same address. Therefore, the basic operation is the same as that of the packet switch shown in FIG.

〔The invention's effect〕

As described above, the present invention uses the associative memory having the symbol string matching function in the shared memory circuit,
It is not necessary to divide the usage of the memory for each destination, and it is possible to store packets of any destination in the memory as long as there is a free area in the memory. Therefore, it is possible to significantly reduce the memory capacity as compared with the conventional method, and it is possible to provide an inexpensive packet switcher with less economical burden than the conventional method. In the conventional method, this difference increases in memory capacity in proportion to the number of lines, and therefore becomes noticeable in packet switching that accommodates a large number of lines.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram showing a basic structure of a packet on a memory, and FIG. 3 is a structure showing how packets are stored in an associative memory. FIG. 4 is a block diagram of a second embodiment of the present invention,
FIG. 5 is a block diagram showing how packets are stored in the shared memory circuit of the packet switch shown in FIG. 1,2,3 …… Input line, 4 …… Multiplex circuit, 5 …… Input time division bus, 6 …… Shared memory circuit, 7 …… Output time division bus, 8 …… Separation circuit, 9,10,11 ...... Output line, 12 …… Write control circuit, 13 …… Read control circuit, 14,16 ・ ・ ・ Associative memory circuit, 15 …… Memory circuit.

Claims (2)

[Claims] 1. A multiplexing circuit for time-division and multiplexing of packets input from a plurality of input lines on one bus, and an input time division bus for transferring output information from the multiplexing circuit.
The packets on the input time-division bus are sequentially written and written in the empty area of the memory. The packets are output corresponding to the destination by referring to the additional information in the packet, and after the output, the read packets are stored. A shared memory circuit having a function of freeing a reserved area, and packet information sequentially read from the shared memory circuit in correspondence with the destination is put in the time slot position of the output line corresponding to the destination of this packet. In the packet switch having an output time division bus for multiplexing and transferring different packets and a separation circuit having a function of outputting a packet on the output time division bus from the time slot position to a corresponding output line, the shared memory The circuit, when given a particular symbol sequence, compares it with the packet information stored in the shared memory circuit. Has a symbol string collating function of outputting the result of the comparison as a coincidence or non-coincidence signal and at the same time outputting the address on the shared memory circuit in which the coincident packet information exists as a packet storage address when the coincidence is obtained. A content addressable memory circuit, and assigning 1 bit in the packet storage address in the shared memory circuit to a display bit indicating empty space,
The empty address in the packet storage address is detected by comparing and collating all the bits in the display bit area with the empty value, and the input packet including the destination information is written and the display bit is blocked. When the packet is read, a comparison and collation operation is performed with the value of the destination output to the area storing the destination information in the packet, and the packet having the same destination as the output destination exists. By detecting the address and reading the information of this address, the packets are sequentially output to the output line corresponding to the output destination, and after the packet output, the value of the display bit is rewritten to the empty state and the packet to be input next is written. A packet switch characterized by being operable. 2. A shared memory circuit writes only the additional information including the destination information in the packet information and accumulates it, and compares and collates the display bit indicating the vacancy to know the writable address of the packet and compare it to the destination information. A transfer storage memory having a function of being able to know a storage address of a packet of a specific destination by collation, and a memory circuit having a function of specially writing and storing communication information excluding additional information in the packet information. When the packet information is written to the associative memory circuit and the memory circuit, the address of the empty area indicated by the display bit is commonly used, and the additional information and the communication information including the destination information of the packet information, respectively. Of the address obtained from the matching operation of the associative memory circuit at the time of writing and reading. By performing the reading of the packet information from the content-addressable memory circuit and a memory circuit using a scan, the packet switch of claim 1 wherein characterized in that it has a function of sequentially outputting packet information corresponding to the destination.