JPS62137855A - Semiconductor device having multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To suppress the growing of a protruded part on the surface of Al and to reduce the short circuits between upper and lower interconnections, by arranging the interconnection of each layer comprising Al so that the interconnection is held between SiN films having a small difference in thermal expansion coefficient and compression residual stress is imparted owing to the quality improvement by sputtering when the SiN films are formed on the surface of the Al upper layer. CONSTITUTION:At first, an SiO2 or PSG film 1 is formed. Then an SiN film 2 is attached on the film 1. A first interlayer insulating film 3 comprising the SiO2 or PSG film and the SiN film is constituted. Then a lower layer wiring 4 comprising Al is formed in contact with the SiN film on the first interlayer insulating film 3. An SiN film 5 is formed by using a sputtering apparatus. Thus quality improvement of the Al surface is achieved by a work hardening phenomenon, and compression stress is yielded. The stress brings about the effect, by which stress yielded in heat treatment in succeeding processes is alleviated. Then an SiO2 or PSG film 6 is deposited on the SiN film 5. Thus a second interlayer insulating film 7 comprising the SiO2 or a PSG film and the SiN film is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field to which the invention pertains The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure.

(1) Prior art and its problems In a semiconductor device having a multilayer wiring structure, the wirings in each layer are insulated by interlayer insulation and an insulating film.

Conventionally, At was used as the wiring material and S was used as the interlayer insulating film.
iOz or PSG (Phospho-8i
It was common to use licateQlass). However, as shown in the table below, At and 8102
Since there is a large difference in thermal expansion coefficient from that of PSG, when heat treatment is repeated in the post-process, the overall expansion of kl is suppressed by the interlayer insulating film.

Table 1 Therefore, At tries to release the stress σ) by local expansion, and as a result, protrusions grow on the At surface, which destroys the interlayer insulation ha and causes 7-yotes between the interconnects. Reliability had been reduced. In order to prevent the above problem, thickening the interlayer insulating film may not be a solution, since the step becomes steep in the through-hole area where the upper layer wiring makes contact with the lower layer wiring, creating a risk of disconnection of the wiring. There wasn't.

? N. Purpose of the Invention The present invention has been made in view of the above-mentioned conventional circumstances, and it is an object of the present invention to provide a semiconductor device having a multilayer wiring structure that is free from the risk of short-circuiting between upper and lower layer wirings and disconnection of upper and lower interlayer wirings. be.

(2) Structure of the Invention The present invention provides a semiconductor device having a multilayer wiring structure in which wiring in each layer of At is sandwiched between upper and lower interlayer insulating films, in which each layer is formed using a sputtering device. It is characterized by

+n Effect of the Invention According to the above structure, the wiring in each layer made of At is sandwiched between SiN films having a small difference in coefficient of thermal expansion from At, so that the overall expansion of At during heat treatment is considerable. It will be allowed up to the extent of 5i, and the At soil layer surface is 5i
When forming Nt9, modification is performed by sputtering and compressive residual stress is applied.

(F) Embodiment of the Invention The drawings show a preferred embodiment of the invention, and show the structure of a semiconductor device having a multilayer wiring structure in stages of manufacture. First, as shown in (1), SiO3 or PSG
A first interlayer insulating film 6 made of S + 02 or T'SG film and SiN film is formed by depositing a SiN film 2 thereon.

Here, the thermal expansion coefficient of SiN is 2.5X10/'C
and has an intermediate value between the above-mentioned At and S i 02 or P S G.

(2) A lower layer wiring 4 made of Al is formed on the first interlayer insulating film in contact with the SiN film.

(3) At glass 7-1 lower layer wiring 4 (n upper 1c
S i lNi1iJ 5 It is formed using a lath batter apparatus. By sputtering SiN onto the A1 surface, the At surface is modified by a work hardening phenomenon and compressive stress is generated.

This has the effect of alleviating stress generated during heat treatment in the post-process.

(8+02 or P
A film 6 made of SG is attached, and S io 2 or I'
A second interlayer insulating film 7 made of an SG film and a SiN film is formed.

Here, the thickness of the interlayer insulating film 5.7 consisting of the SiO3 or PSG film and the SiN film is such that since the At wiring material is covered with the SiN film, a larger expansion of At than in the conventional structure is allowed during heat treatment. Since the stress generated during heat treatment of A4 during heat treatment is alleviated by SiN sputtering, the generation of protrusions on the surface of A4 is suppressed. It is fine if it is thinner than the thickness of . In addition, the figure shows a state in which the second interlayer insulating film 7 is formed as a clear square protrusion on the lower layer wiring, which may also be At, but in the actual processing process, the tapering force of the protrusion is distorted. The interlayer dielectric film is significantly planarized.

Through the above steps, up to the second interlayer insulating film is formed, and the above steps are further repeated to form a semiconductor device having a multilayer wiring structure.

(G) Effects of the Invention As described above, according to the present invention, the wiring in each layer, including A and T, has a higher thermal expansion property than Al and PSG, which are interlayer insulating film materials commonly used in the past. Since it is disposed between SiN films having a small difference in coefficients, the expansion of kt during heat treatment is allowed to be larger than before. In addition, the sputtering during the formation of the AtJ single-layer SiN film causes modification by work hardening phenomenon and generates compressive stress, which has the effect of relieving the stress generated during heat treatment.For these reasons, the protrusion growth on the At surface This reduces the risk of short circuits between upper and lower layer wiring. Also, as mentioned above, SiN and S r 02 or P
The interlayer insulating film made of SG has the effect of suppressing the growth of protrusions on the surfaces of A and t, so the thickness of each interlayer insulating film is equal to that of the conventional S.
The thickness can be made thinner than the interlayer insulating film made only of i02 or PSG film, and this prevents the step from becoming steep in the through-hole area where the upper-layer wiring makes contact with the lower-layer wiring, and prevents disconnection of the wiring. It has the effect of preventing

[Brief explanation of drawings]

The figures are schematic diagrams showing the structure of a semiconductor device having a multilayer wiring structure according to the present invention in manufacturing steps. 1.6...5iO8 or PSG film, 2,5...S
iN film, 6.7...interlayer insulating film, 4...wiring that can also be At. Patent amount, Applicant: Sumitomo Electric Industries, Ltd. (5 others) Procedural amendment Written on March 3, 1986 1. Case description 1985 Patent Application No. 279998 2. Name of the invention Multilayer wiring structure Semiconductor device 3 having the following: Relationship with the case of the person making the amendment Address of the patent applicant. Name (213) Sumitomo Electric Industries, Ltd. 4, Agent Drawing 6, Contents of amendment (1) The statement “Diagram is” in Line 5 of No. 7 TX of the Statement of Application M is shown in rtlS1 Diagrams (1) to (4) I am corrected. (2) The drawings in the application are corrected as shown in the attached two figures. (Enter "Figure 1") That's all

Claims (2)

[Claims] (1) In a semiconductor device having a multilayer wiring structure in which wiring in each layer made of Al is sandwiched between upper and lower interlayer insulating films, the surfaces where the upper and lower interlayer insulating films sandwiching the wiring in each layer are in contact with the wiring, respectively. 1. A semiconductor device having a multilayer wiring structure, characterized in that a SiN film is formed above the wiring, and the SiN film above the wiring is formed using a sputtering device. (2) A semiconductor device having a multilayer wiring structure according to claim 1, wherein the interlayer insulating film is composed of a SiO_2 or PSG film and the SiN film.