JPS63142834A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63142834A JPS63142834A JP29124386A JP29124386A JPS63142834A JP S63142834 A JPS63142834 A JP S63142834A JP 29124386 A JP29124386 A JP 29124386A JP 29124386 A JP29124386 A JP 29124386A JP S63142834 A JPS63142834 A JP S63142834A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tiw
- aluminum alloy
- metal wiring
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims abstract description 5
- 230000008018 melting Effects 0.000 claims abstract description 5
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000001755 magnetron sputter deposition Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000001459 lithography Methods 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910001132 Ar alloy Inorganic materials 0.000 description 1
- 229910000711 U alloy Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000012209 synthetic fiber Substances 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置に係るものであり、特に。[Detailed description of the invention] <Industrial application field> The present invention relates to semiconductor devices, and particularly to semiconductor devices.
その金属配線の構造に関するものである。This relates to the structure of the metal wiring.
〈従来の技術〉
半導体集積回路装置は高性能、高密度化に伴り金属配線
は多層にレイアウトされる。<Prior Art> As semiconductor integrated circuit devices become more sophisticated and denser, metal wiring is laid out in multiple layers.
第2図に従来の半導体集積回路装置の構造及びその製造
プロセス?示す。Figure 2 shows the structure of a conventional semiconductor integrated circuit device and its manufacturing process. show.
一@2図fat
半導体基板l上に素子分離用フィールド酸化膜2を形成
し、その後、ゲート酸化膜3.ゲート電極4及び層間絶
縁膜5の形成を行う。Figure 1@2: A field oxide film 2 for element isolation is formed on a semiconductor substrate 1, and then a gate oxide film 3. Gate electrode 4 and interlayer insulating film 5 are formed.
・第2図(bl
金属配線形成用の金属膜(Ai又はA1合金膜)6′を
形成する。- Figure 2 (bl) A metal film (Ai or A1 alloy film) 6' for forming metal wiring is formed.
・第2図fcl
レジスト塗布後、露光、現像ヲ経てマスク7を形成する
。・FIG. 2 fcl After resist coating, a mask 7 is formed through exposure and development.
一第2図[dl
その後、リアクティブイオノエツチング2行い金属配線
6を形成する。クリーニング後、絶縁膜8を形成し、熱
処理を行った後、第2層目の金属配線9を形成する。な
お、単層配線の場合は、絶縁膜形成後、最終の熱処理を
行う。2 [dl] Thereafter, reactive ion etching 2 is performed to form metal wiring 6. After cleaning, an insulating film 8 is formed, heat treatment is performed, and then a second layer of metal wiring 9 is formed. Note that in the case of single-layer wiring, a final heat treatment is performed after forming the insulating film.
〈発明が解決しようとする問題点〉
し75)シながら、上記従来の半導体装置には以下に示
す問題点があった。<Problems to be Solved by the Invention> 75) However, the above-mentioned conventional semiconductor device has the following problems.
金属配線上の絶縁膜形成、熱処理で金属膜表面る。Insulating film is formed on metal wiring, and the metal film surface is heated through heat treatment.
さらに、エレクトロマイグレーションも微細化に伴い大
きな問題となる。Furthermore, electromigration also becomes a big problem with miniaturization.
本発明は上記問題点を解決することを目的としているも
のである。The present invention aims to solve the above problems.
〈問題点を解決するための手段〉
金属配線の構造に、Ar膜又はAr合金膜上に高融点金
属又はそのシリサイドから成る被覆膜を形成し之構造と
する。さらに、上記被覆膜を圧縮圧力を持つ膜とする。<Means for Solving the Problems> The structure of the metal wiring is such that a coating film made of a high melting point metal or its silicide is formed on an Ar film or an Ar alloy film. Furthermore, the coating film is a film having compressive pressure.
く作 用〉
高融点金属又はそのシリサイドから成る固い被覆膜を設
けることによりヒロックの発生が抑えられる。上記被覆
膜を圧縮応力を持つ膜とすることにより、Ar膜、Aノ
合金膜を押え込む力が作用することになるので、ヒロッ
ク発生防止に対してより効果的なものとなる。また、同
被覆膜を設けることによ、9Aノの移動が抑えられるの
で、ボイド発生、エレクトロマイグレーションに対して
も効果がある。Effect> The formation of hillocks can be suppressed by providing a hard coating film made of a high melting point metal or its silicide. By making the above-mentioned coating film a film having compressive stress, a force that presses down the Ar film and the A-alloy film will act, which will be more effective in preventing the occurrence of hillocks. Further, by providing the same coating film, the movement of 9A can be suppressed, so it is effective against void generation and electromigration.
〈実施例〉 以下、実施例に基づいて未発明を詳細に説明する。<Example> Hereinafter, the invention will be described in detail based on examples.
第1図は本発明の一実施例の構造及びその製造プロセス
を示す図である。FIG. 1 is a diagram showing the structure and manufacturing process of an embodiment of the present invention.
・第1図(a)
半導体基板11上に素子分離用フィールド酸化膜In形
成し、その後、ゲート酸化膜13゜ゲート電極14及び
層間絶縁膜15を形成する。・FIG. 1(a) A field oxide film In for element isolation is formed on the semiconductor substrate 11, and then a gate oxide film 13°, a gate electrode 14, and an interlayer insulating film 15 are formed.
層間絶縁膜15上に、DCマグネトロンスパッタリング
法により、まずA1合金(例えば、Al・1%Si)膜
16を形成する。その後。First, an A1 alloy (for example, Al/1% Si) film 16 is formed on the interlayer insulating film 15 by DC magnetron sputtering. after that.
同一真空中に於いて、上記A1合金膜16上にDCマグ
ネトロンスパッタリング法により、形成膜が圧縮応力を
もつ条件で厚さ約250λのTiW膜17を形成する。In the same vacuum, a TiW film 17 with a thickness of about 250λ is formed on the A1 alloy film 16 by DC magnetron sputtering under conditions that the formed film has compressive stress.
TiWの場合、膜中の内部応力はAr圧及びパワーによ
って決定される〔第3図[al 、 fb)参照)。こ
こで、Ar圧8 mtorr 、パワーIKwの条件を
選ぶことにより、 5 X l O″dyn、/s”
の圧縮応力を持つTiW膜を形成することができる。In the case of TiW, the internal stress in the film is determined by the Ar pressure and power (see Figure 3 [al, fb)]. Here, by selecting the conditions of Ar pressure 8 mtorr and power IKw, 5 X l O"dyn,/s"
It is possible to form a TiW film having a compressive stress of .
・第1図ibl
リソグラフィ一工程により金属配線(Al合金膜+Ti
W@)1gを形成する。その後、絶縁膜19を形成し、
熱処理を行う。・Figure 1 ibl Metal wiring (Al alloy film + Ti
W@) Form 1g. After that, an insulating film 19 is formed,
Perform heat treatment.
通常、第4図に示すように、Ar・Si単層であればヒ
ロックが形成されるが、TiW/Aノ・Siの構造のも
のは全くヒロックが形成されない。Normally, as shown in FIG. 4, hillocks are formed in a single layer of Ar.Si, but no hillocks are formed in a structure of TiW/A-Si.
ま*、Tiwの膜厚が厚いと、Ar・5 i (7)側
啼方向にヒロック(Lateral Hillock
)が発生するが、250〜5 ooiの膜厚を選ぶこと
により、これも抑えることができる。*If the TiW film is thick, Ar・5 i (7) Lateral hillocks will occur in the lateral direction.
) occurs, but this can also be suppressed by selecting a film thickness of 250 to 5 ooi.
従来の技術に於いて、金属配線形成用にAr・Siの様
な反射率の大きな材料を用いた場合。In the conventional technology, when a material with a high reflectance such as Ar/Si is used for forming metal wiring.
後のフォトリソグラフィ一工程で金属膜表面での光の反
射によりレジストがオーバ露光状態になり、マスク幅に
比べ小さくなったり1局所的に光力集光し、パター/が
到くなっ之シする現象が大きな問題である。その様子を
第5図(上面図、全面にAl・Si膜が形成されている
)に示す。矢印は乱反射光の経路を示している。During the subsequent photolithography process, the resist becomes overexposed due to the reflection of light on the metal film surface, and the resist becomes smaller than the mask width, or the light is concentrated locally, causing the pattern to become blurred. phenomenon is a big problem. The situation is shown in FIG. 5 (top view, an Al/Si film is formed on the entire surface). The arrow indicates the path of the diffusely reflected light.
71がマスク7のくびれ部分である。71 is the constriction of the mask 7.
未発明のように、Ar・Si膜上にTiW膜を形成すれ
ば、第6図に示すように、Ar・Si上TiW膜の反射
率は約50%と半減し、上記のようなハレーション防止
にも非常に効果がある。If a TiW film is formed on an Ar/Si film as previously proposed, the reflectance of the TiW film on Ar/Si will be halved to approximately 50%, as shown in Fig. 6, and the halation prevention as described above will be reduced. is also very effective.
上記実施例に於いては、A1合金膜16上にTiW膜1
7を形成した後、微細加工(エツチング加工)を行って
金属配線18を形成してbるが、Aノ合金膜(例えば、
Al・1%Si膜)形成→微細加工後、通常の洗浄工程
を経て。In the above embodiment, the TiW film 1 is placed on the A1 alloy film 16.
After forming 7, microfabrication (etching) is performed to form metal wiring 18.
Formation of Al/1%Si film) → After microfabrication, go through the normal cleaning process.
CVD法等によシ、高融点金属又はそのシリサイドから
成る被覆膜を形成するようにしてもよい。例えば、WF
a+H2ガスを用いると、400℃前後の温度、0.1
〜1torr の圧力で、Ai合金膜上に選択的にW膜
を形成することができる。この場合、第7図に示すよう
に。A coating film made of a high melting point metal or its silicide may be formed by CVD or the like. For example, W.F.
When using a+H2 gas, the temperature is around 400℃, 0.1
A W film can be selectively formed on an Ai alloy film at a pressure of ~1 torr. In this case, as shown in FIG.
A1合金膜22の上面だけでなく側壁知もW膜23が形
成されるため、あらゆる方向のヒロックを抑制できる。Since the W film 23 is formed not only on the upper surface of the A1 alloy film 22 but also on the side walls, hillocks can be suppressed in all directions.
なお、同図において、21は層間絶縁膜である。In addition, in the figure, 21 is an interlayer insulating film.
〈発明の効果〉 以上詳細に説明したように、未発明によれば。<Effect of the invention> As explained in detail above, according to the invention.
金属配線にヒロックが生じず、絶縁膜の絶縁特性。No hillocks occur in metal wiring, and the insulation properties of the insulation film.
耐湿性の劣化を防止することができる。また、Aノの再
結晶化に伴うボイド発生、エレクトロマイグレーション
も抑えることができるので、金属配線の断線等も防止す
ることができるものである。Deterioration of moisture resistance can be prevented. Moreover, since the generation of voids and electromigration accompanying the recrystallization of A can be suppressed, it is also possible to prevent disconnection of metal wiring, etc.
以上のように、未発明は、半導体装置の高密度化、多層
配線化等に対して株めて有効な技術を提供するものであ
る。As described above, the present invention provides a technology that is extremely effective for increasing the density of semiconductor devices, multilayer wiring, and the like.
第1図は未発明の一実施例の構造及びその製造プロセス
を示す図、第2図は従来の半導体集積回路装置の構造及
びその製造プロセスを示す図、第3図はDCマグネトロ
ンスパッタリング法によりTiW膜を形成する場合に於
ける形成条件と膜中の内部応力との関係を示しt図、第
4図は金属配線がAノ・Si単層の場合とTiW/Aノ
・Si構造の場合のそれぞれについてヒロック密度ヲ示
した図、@5図は従来技術に於いてハレーションによシ
マスフ幅が細くなることを示した図、第6図はTiW膜
の反射率を示した図、第7図は他の実施例の説明に供す
る断面図である。
符号の説明
16:、U合金膜、夏7:TiW膜、18:合繊配線、
22:Aノ合金膜、23:W膜。
代理人 弁理士 杉 山 毅 至(他1名)o
−0
品Cヘベ憐′町FIG. 1 is a diagram showing the structure and manufacturing process of an embodiment of the invention, FIG. 2 is a diagram showing the structure of a conventional semiconductor integrated circuit device and its manufacturing process, and FIG. 3 is a diagram showing the structure of a conventional semiconductor integrated circuit device and its manufacturing process. Figure 4 shows the relationship between the formation conditions and the internal stress in the film when forming the film, and shows the relationship between the metal wiring in the case of an A-Si single layer and the TiW/A-Si structure. Figure 5 shows the hillock density for each, Figure @5 shows how the strip width narrows due to halation in the conventional technology, Figure 6 shows the reflectance of the TiW film, and Figure 7 FIG. 7 is a cross-sectional view for explaining another embodiment. Explanation of symbols 16: U alloy film, Summer 7: TiW film, 18: Synthetic fiber wiring,
22: A alloy film, 23: W film. Agent: Patent attorney Takeshi Sugiyama (and 1 other person) o
-0 Product C Hebe Ren'cho
Claims (2)
シリサイドから成る被覆膜を形成した構造の金属配線を
設けたことを特徴とする半導体装置。(1) A semiconductor device characterized in that a metal wiring is provided with a structure in which a coating film made of a high melting point metal or its silicide is formed on an Al film or an Al alloy film.
とする、特許請求の範囲第(1)項に記載の半導体装置
。(2) The semiconductor device according to claim (1), wherein the coating film is a film having compressive stress.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29124386A JPS63142834A (en) | 1986-12-05 | 1986-12-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29124386A JPS63142834A (en) | 1986-12-05 | 1986-12-05 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63142834A true JPS63142834A (en) | 1988-06-15 |
Family
ID=17766330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29124386A Pending JPS63142834A (en) | 1986-12-05 | 1986-12-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63142834A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03240234A (en) * | 1990-02-19 | 1991-10-25 | Matsushita Electron Corp | Semiconductor device |
CN115323336A (en) * | 2022-08-10 | 2022-11-11 | 福建兆元光电有限公司 | Sputtering method of LED chip |
-
1986
- 1986-12-05 JP JP29124386A patent/JPS63142834A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03240234A (en) * | 1990-02-19 | 1991-10-25 | Matsushita Electron Corp | Semiconductor device |
CN115323336A (en) * | 2022-08-10 | 2022-11-11 | 福建兆元光电有限公司 | Sputtering method of LED chip |
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