JPH03227022A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avert the unfavorable effect of an upper layer Al wiring in the case of forming an interlayer film on the coverage while avoiding the deterioration in the humidity resistance in the case of forming a passivation film by a method wherein a semiconductor device is structured of a laminated layers comprising WSi wiring formed on an Al or Al alloy wiring while the width of the WSi wiring is made narrower than that of the Al or Al alloy wiring. CONSTITUTION:After the formation of an SiO2 film 3 on an Si substrate 4, an Al wiring 2 and a WSi wiring 1 are continuously formed in the same chamber and then the width of the WSi wiring 1 is made narrower than that of the Al wiring 2 by lithography. Accordingly, when an SiO film is formed on the WSi wiring 1, no eaves is made, furthermore, when a passivation film is formed, the film thickness thereof is not decreased in any positions at all thereby enabling the deterioration in the humidity resistance thereof to be avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, and particularly to EM (electromigration) and SM (stress migration).
The present invention relates to a wiring structure that is resistant to corrosion and does not adversely affect interlayer films or passivation films.

[Conventional technology]

Conventionally, this type of semiconductor device has used Ap as an electrode wiring material, but serious reliability failures such as EM and SM have occurred with recent integration of elements. As one solution to this problem, a method has been proposed in which a layered structure is formed in which WSi is spread over Aj. However, when the laminated structure wiring is microfabricated using an anisotropic dry etching device, an eaves approximately as thick as the film is generated in the WSil above Ap2, as shown in FIG. FIG. 3 shows a state in which the SiO film 5 is provided on the wiring with the canopy shown in FIG. As is clear from FIG. 3, the eaves portion of WSil also creates an eave on the SiO film 5. When a multilayer wiring structure is adopted, an Al2 wiring is provided on this SiO film 5. For comparison, FIG. 4 shows an Al single layer wiring structure in which WSi is not provided on AjI, and in this case no eaves are formed in the SiO film 5.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, due to reliability issues, it is necessary to use a laminated structure in which WSi is spread over Ag; I for element integration. When microfabrication is performed using WSi, an overhang may occur in WSi.
This may have an adverse effect on the coverage of l-wirings, or when a passivation film is formed, the film thickness may become thinner in some areas, leading to deterioration in moisture resistance, which is a cause for concern regarding reliability.

[Means to solve the problem]

The present invention provides a semiconductor device in which the wiring structure of a surface electrode for a semiconductor device has a laminated structure in which WSi is formed on Ag or A1 alloy, and the wiring width of WSi is Ag or A1 alloy.
It is characterized by having a wiring width equal to or less than that of No. 1 alloy.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal cross-sectional view of one embodiment of the present invention. After forming a Si 02 film 3 on a Si substrate 4, it was preheated using a sputtering device at a power of 5 KW, a pressure of 1 5 mTorr, and a preheating temperature of 200 mTorr.
This is the result of sequentially forming Ag2 and WSil in the same chamber under the conditions of 200° C. and 200° C., and then performing lithography. Lithography is PF-7550
After applying 2.5 μm of BDye-containing resist, exposure was performed at 500 mW and 720 m5ec using a stepper, and TMAH (Te-tra Methyl Ammon
ium Hydroxide) type developer, and after post-beta at 130°C, fluorine type gas was mixed with chlorine type gas and anisotropic dry etching was performed at 800 W and 10 Pa, and then CF4.02 type gas was used. 800W
, WSi by isotropic dry etching at 80 Pa for 10 seconds.
Only the side was etched. At this time, since it is known that the etch rate of WSi is about 9000 A/min, the side etching rate of WSi is about 1500 A/min. Thereafter, the resist was oxidized and removed using oxygen plasma at 800 W for 150 minutes.

In this way, the width of the WSi in this example is smaller than the width of the Ag2 wiring, so even if a SiO film is provided on it, no overhang will occur, and furthermore, even if an Ap wiring is formed on it, it will be smaller than the width of the Ag2 wiring. There are no such drawbacks.

Note that in the above example, WSi was formed by sputtering, but
WSi may be formed by low pressure CVD.

The conditions for forming WSi by low pressure CVD are that the raw material gas is WF6.
, SiH4, H2 mixed gas at a growth pressure of 100 rt.
rTorr and growth temperature of 380°C.

〔Effect of the invention〕

As explained above, in the semiconductor device of the present invention, the wiring structure is formed using WS on Ag or Ag alloy in the surface electrode wiring.
It has a laminated structure with i formed, and the wiring width of WSi is A.
1 or A, R alloy wiring width, even if an interlayer film is formed using a plasma CVD 5iO film or a plasma CVD 5iN film, it will not adversely affect the coverage of the upper layer AI2 wiring, and when forming a passivation film, the film thickness can also be reduced. It has the advantage that moisture resistance does not deteriorate because there are no areas where the film becomes thin.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of the conventional technique, FIG. 3 is a vertical cross-sectional view showing the state in which 510M is formed on the surface of the conventional technique, and FIG. 4 is a vertical cross-sectional view of the conventional technique. Conventional technology WSi
FIG. 2 is a vertical cross-sectional view of a structure without 1...WSi, 2...Al, 3...5i02 film,
4...Si substrate, 5...SiO film.

Claims (1)

[Claims] The wiring structure of the surface electrode is Al (aluminum) or A
1. A semiconductor device having a laminated structure in which WSi (tungsten silicide) is formed on an L alloy, wherein the wiring width of the WSi is equal to or less than the wiring width of the Al or Al alloy.