JPS62137791A - タイミング信号チェック方式 - Google Patents
タイミング信号チェック方式Info
- Publication number
- JPS62137791A JPS62137791A JP60277430A JP27743085A JPS62137791A JP S62137791 A JPS62137791 A JP S62137791A JP 60277430 A JP60277430 A JP 60277430A JP 27743085 A JP27743085 A JP 27743085A JP S62137791 A JPS62137791 A JP S62137791A
- Authority
- JP
- Japan
- Prior art keywords
- timing
- circuit
- signal
- check
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Memory System (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60277430A JPS62137791A (ja) | 1985-12-10 | 1985-12-10 | タイミング信号チェック方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60277430A JPS62137791A (ja) | 1985-12-10 | 1985-12-10 | タイミング信号チェック方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62137791A true JPS62137791A (ja) | 1987-06-20 |
JPH0375908B2 JPH0375908B2 (enrdf_load_stackoverflow) | 1991-12-03 |
Family
ID=17583450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60277430A Granted JPS62137791A (ja) | 1985-12-10 | 1985-12-10 | タイミング信号チェック方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62137791A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007087467A (ja) * | 2005-09-20 | 2007-04-05 | Elpida Memory Inc | データ転送動作終了検知回路及びこれを備える半導体記憶装置 |
-
1985
- 1985-12-10 JP JP60277430A patent/JPS62137791A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007087467A (ja) * | 2005-09-20 | 2007-04-05 | Elpida Memory Inc | データ転送動作終了検知回路及びこれを備える半導体記憶装置 |
US8713247B2 (en) | 2005-09-20 | 2014-04-29 | Hiroki Fujisawa | Data transfer operation completion detection circuit and semiconductor memory device provided therewith |
Also Published As
Publication number | Publication date |
---|---|
JPH0375908B2 (enrdf_load_stackoverflow) | 1991-12-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |