JPS62137791A - Checking system for timing signal - Google Patents

Abstract

PURPOSE:To check the titled timing signal in a no-operation time by providing a register which shifts an operation command at the timing of a machine cycle and generating a NP timing check signal when the register is not busy. CONSTITUTION:A timing circuit 110 generates timing signals related to reading and writing operations, etc. based on an operation command CMD. A command shift register circuit 120 shifts successively the input state of the command CMD at each shift stage. A busy checking circuit 130 generates the NP timing check signal which checks the timing signals related to the no-operation when the circuit 120 is not busy. A timing check circuit 140 checks the timing signal related to the no-operation when the NP timing signal is received.

Description

[Detailed Description of the Invention] [Summary] In a method of checking each timing signal for reading (RD), writing (WT), etc. to memory, RD, WT, etc.
A register is provided to shift an operation command (CMD) indicating ``1'' at machine cycle timing, and when the register is not busy, an NP timing check signal is generated to check the timing signal regarding no-operation. As a result, RD, W
Even when each timing signal such as T is formed based on CMD, the timing signal can be checked not only during each operation of RD, WT, etc., but also during no operation.

[Industrial application field]

The present invention relates to a method for checking timing signals for reading, writing, refreshing, etc. to a memory, and in particular,
The present invention relates to a timing signal checking method that is improved so that the timing signal can also be checked during no-operation conditions.

[Conventional technology]

In order for each operation such as read, write, refresh, etc. to be performed normally on the memory, each timing signal for read, write, refresh, etc. applied to the memory must be error-free.

For this reason, the presence or absence of errors in each read, write, and refresh timing signal is checked.

FIG. 7 is a block diagram showing a conventional timing signal control system.

In FIG. 7, 210 is a timing signal generation circuit;
Receives operation commands CMD for read, write, and refresh sent from the control unit, and performs read, write, and refresh operations.
RAS (RowAddress 5trobe) corresponding to timing signals related to write and refresh
, CA S (Column Address Str.

It generates read (RD), write (WT), and refresh (RF) timing check signals.

In the timing signal generation circuit 210, 211 is a command shift register circuit, which receives an operation command C.
The MDs are sequentially shifted at the timing of the machine cycle.

212 is a command decoder that decodes each operation command input from the command shift register 211 and performs read, write, and refresh operations.RAS, CAS, and WE correspond to each timing signal of RD, WT, and RF. At the same time, RD,
Generates timing check signals for WT and RF.

220 is a timing check circuit, which connects RD, WT and R.
When each timing check signal of F is added, RD,
RAS, C in each timing signal of WT and RF
It is checked whether AS and WE are in a predetermined state corresponding to read, write, and refresh, and if they are not in a predetermined state, an error signal is generated.

As described above, the RAS, CAS, and WE of each timing signal of RD, WT, and RF are checked, and the correct timing signal is applied to the memory, so that each desired read, write, or refresh operation is performed normally. I'm doing it like that.

However, when each timing signal is generated from the operation command CMD, the timing signals are not checked during a no-operation when no read, write, or refresh is performed. This is because the RAS, CAS, and RF timing signals are all off during no operation, so there was no good way to create a timing check signal.
- This is because, unlike during read, write, and refresh, it is not essential to perform a timing check during no-operation.

[Problem that the invention seeks to solve]

Conventional operation commands CMD to RD.

In the timing signal check method for generating each of the WT and RF timing signals, as described above, the timing signals are not particularly checked during no-operation.

However, if there is an error in the no-operation timing signal and a read, write, or refresh timing signal is erroneously generated, there is a risk that these erroneous timing signals will have an adverse effect on the memory. In particular, in the case of a memory device consisting of a combination of multiple memories, such as a memory device configured with multiple memory cards,
There is a risk that each memory will have an adverse effect on each other.

Conventionally, timing checks were not performed during no-operation, so these dangers could not be naturally prevented.

The present invention provides RD from operation commands.

An object of the present invention is to provide a timing signal check method for generating WT and RF timing signals, which checks the timing signals even during no operation.

[Means for solving problems]

The means taken by the present invention to solve the above-mentioned problems in the conventional timing signal checking system will be explained with reference to FIG.

FIG. 1 is a block diagram showing the configuration of the present invention.

In FIG. 1, 110 is a timing circuit with leads,
Timing signals related to operations such as read and write are generated based on an operation command CMD that instructs write and the like.

A command shift register circuit 120 sequentially shifts the input operation command CMD at the timing of a machine cycle and outputs the state of the operation command CMD at each shift stage.

A busy check circuit 130 generates a signal (NP timing check signal) for checking a timing signal regarding no-operation when the command shift register circuit 120 is not busy. Note that the command shift register circuit 120 is busy when an operation command for operations such as read and write is being generated.

140 is a timing check circuit that checks timing signals related to operations such as read and write, and
When the NP timing check signal is received, the timing signal regarding no operation is checked.

Note that although the command shift register circuit 120 is shown separately from the timing circuit 110, the timing circuit 1
If there is a configuration in 10 that has a function similar to that of the command shift register circuit 120, this also includes the case where that configuration is shared as the command shift register circuit 120.

[For production]

The operation shown in FIG. 1 will be explained with reference to FIG. 2.

Figure 2 shows the RA of each timing signal when reading, writing, and refreshing within two machine cycles.
This shows an example of each waveform of S, CAS, and WE.
(al is the RD or WT timing signal, (b) is the RF
Timing signal, (C) is no operation (NOP)
) for the timing signals RAS, CAS and W
Each waveform of E is shown.

CK l'' CK 4 is each clock, and tl and t2 between each clock form one machine cycle.

Refresh is CA S Before RA
The case of 5Refresh is shown.

Note that FIG. 2 is shown as a reference for understanding the operation of the present invention, and the present invention is not limited to the case of each timing signal shown in FIG.

The timing circuit 110 operates as shown in FIG. 2 (
a) or (RAS of the timing signal shown in bl,
CAS and WE are generated in synchronization with clock CK. At the same time, the timing circuit 110 performs a machine cycle τ
1 or τ2, etc., outputs an RD timing check signal, a WT timing check signal, or an RF timing check signal depending on a read, write, or refresh operation.

The timing check circuit 140 is RD, WT or RF.
RAS, C of each timing signal of RD, WT or RF at the time when each timing check signal is inputted
The states of AS and WE are checked, and if they are different from predetermined states corresponding to each timing signal, an error signal is output.

During no operation, the command shift register circuit 110 does not generate any operation command CMD for read, write, or refresh at each shift stage.

The busy check circuit 130 is configured so that the command shift register circuit 1
20 detects that it is not busy and outputs an NP timing check signal for performing a timing check regarding no-operation.

When the timing check circuit 140 receives this NP timing check signal, it checks the timing regarding no-operation and determines whether RAS, CAS, and WE are in a predetermined state (all off) at the time of no-operation. and generates an error signal if something is not in the predetermined state.

As described above, according to the present invention, it is possible to generate an NP timing check signal from an operation command with a simple configuration and check the timing regarding a no-operation.

[First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. 2 to 4. The first embodiment reads in two machine cycles;
This is an example in which writing and refreshing are performed.

FIG. 3 is an explanatory diagram of operation commands, and FIG. 4 is a block diagram showing the configuration of the first embodiment. Regarding FIG. 2, it is as already explained.

(A) Configuration of the first embodiment In FIG. 3, CM D o and CM D l are operation commands, which are "10 ”, “11”, “01” and “OO'.

In FIG. 4, the timing circuit 110, command shift register circuit (C3RC) 120, busy check circuit, and timing check circuit 140 are as described in FIG.
CL 20 is a C3RC in timing circuit 110
It is shared with

The timing circuit 110 includes a C5RC 120, a command decoder 111, and flip-flops (FF) 112 to 1.
It is equipped with 14.

In the C3RC12Q, 121 and 122 are inverters that invert CM Do and CM D 1 and input them to the command decoder 111. 123 to 126 are flip-flops (FF), FF123 and 125 are CM
D o is sequentially shifted according to the clock CK, and FF12
4 and 126 sequentially shift CM D + according to the clock CK. Each Q output of the FFs 123 to 126 is input in parallel to a busy check circuit 130. FF123
The inverted outputs of 0 to 126 are input to the command decoder 111.

The command decoder 111 decodes CM Do and CM D 1 of each shift stage sequentially received from the inverters 121 to 122 and FFs 123 to 126 of the C3RC 120, and performs read, write, refresh, and NO signals as shown in FIG. Generates RAS, CAS, and WE corresponding to each timing signal during operation. Furthermore, the command decoder 111 performs machine cycle 1. in FIG. 2 in response to read, write, and refresh operations. Alternatively, at t2, RD, WT, and RF timing check signals are generated and input to the timing check circuit 140. Note that illustration of a configuration for inputting each CM Do and CMDl at each shift stage of the C3RCI 20 to the command decoder 111 is omitted.

As shown in FIG.
, CAS and WE are output. These RAS, C
Each output of AS and WE is controlled by a timing check circuit 14.
Can also be added to 0.

The busy check circuit 130 is composed of a NOR circuit 131. The NOR circuit 131 includes FF11 of C3RC120.
2 to 114, C M Do at each shift stage
and CM D 1 are input. An NP timing check signal is output from the output terminal of the NOR circuit 131,
The signal is supplied to a timing check circuit 140. C3RC
120 is busy, i.e. CM Do and CM D
When l is a read, write or refresh operation command, the output of the NOR circuit 131 is “0”.
'', and the NP timing check signal is not generated.

When C3RC120 is not busy, that is, CM D.

and when CM D 1 is no operation,
The output of the NOR circuit 131 becomes "1" and an NP timing check signal is generated.

(B) Operation of First Embodiment The operation of the first embodiment will be explained separately during a read, write or reflash operation and during a no-operation.

(B-1) Operation during read, write, and refresh Depending on each read, write, or refresh operation, “
10”, “11” or “Of” CM D.

and CM D1 are input to the C3RC120.

CMD in each shift state of C3RC120.

When the outputs of CMDo and CMD1 are supplied to the command decoder 111, the command decoder 111 decodes CMDo and CMDr to produce the outputs (a) and (b) of FIG.
), RAS, CAS, and W correspond to each timing signal during read, write, and refresh.
Generates E. These RAS.

CAS and WE are also input to timing check circuit 140.

Furthermore, the command decoder 111 performs machine cycle t1.
Or at t2, etc., an RD timing check signal, a WT timing check signal, or an RF timing check signal is generated and applied to the timing check circuit 140 in accordance with a read, write, or refresh operation.

On the other hand, during read, write, and refresh operations, C3R
Since C120 is busy, the busy check circuit 13
From 0 onwards, no NP timing check signal is generated.

The timing check circuit 140 checks whether RD, WT or R is being read, written or refreshed.
RAS of each timing signal of RD, WT or RF at the time when each timing check signal of F is input,
Check the states of CAS and WE, and if they are different from the predetermined states corresponding to each timing signal,
An error signal is output and sent to a control section (not shown).

(B-2) Operation at no-operation At no-operation, CMD o input to C5RC120
and CM D l are both '0'', so C3
The outputs of CMD o and CMD 1 at each shift stage of the RC 120 are both 0'.

Therefore, the RAS output from the command decoder 111
, CAS, and WE are in the off state in every machine cycle, as shown in FIG. 2(C).

Further, each timing check signal of RD, WT, and RF is not generated.

On the other hand, the NOR circuit 131 of the busy check circuit 130 is
C M D o at each shift stage of C3RC120
and CM D t are both “0”, so C3R
The timing check circuit 140 detects that C120 is not busy and generates an NP timing check signal.
Enter.

Upon receiving the NP timing check signal, the timing check circuit 140 checks whether RAS, CAS, and WE are in a predetermined state at the time of no operation, that is, in the off state. If even one of them is in a state other than off, an error signal is generated.

Note that the timing check based on the NP timing check signal can be performed in a machine cycle of τ2. Further, although not shown, an NP timing check signal can also be generated in the machine cycles τ1 and τ3 to perform a timing check regarding no-operation.

As described above, by checking the busy state of the C3RC 120, it is possible to easily generate the NP timing check signal and check the timing signal during no operation.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIGS. 2, 3, 5, and 6. The second example is an example in which reading, writing, and refreshing are performed within three machine cycles.

FIG. 5 is a block explanatory diagram of the configuration of the second embodiment, and FIG. 6 is a waveform diagram of each timing signal RAS, CAS, and WE. 2 and 3 are as already explained.

(A) Configuration of second embodiment In FIG. 5, a timing circuit 110', a command shift register circuit (C3RC) 120', a busy check circuit 130', and a timing check circuit 140' are shown.
As explained in FIG. 1, in the second embodiment, the C3RC 120' is shared with the C3RC in the timing circuit 110', as in the first embodiment.

Further, 110' to 140' and other numerical symbols are also given dashes to distinguish them from the first embodiment.

Inverter 121' and 1 in C3RC120'
22', flip-flop (FF) 123' to 128
' has a three-stage configuration, and their contents are as follows: each inverter (121, 12
2) and FF (123-126).

The command decoder 111' corresponds to the command decoder 111 of the first embodiment (FIG. 4), and decodes CM Do and CM D 1 of each shift stage of the C3RC 120', and reads as shown in FIG. Generates RAS, CAS, and WE corresponding to each timing signal during write, refresh, and no-operation. Furthermore, the command decoder 111' generates RD, WT, and RF timing check signals in machine cycle τ2 in FIG. 6 in response to read, write, and refresh operations, and inputs them to the timing check circuit 140'. .

FFs 112' to 114' correspond to FFs 112 to 114 in the first embodiment (FIG. 4), and as shown in FIG. 6, each RAS, CAS, and Output WE. RAS and CA
S is output through NOT input type AND circuits 117' and 118'.

These RAS, CAS, and WE outputs are also applied to timing check circuit 140'.

FF115' and FF116' generate RAS and CAS during refresh operation. Of course, RAS and CAS during refresh operation are FF123' and FF11.
It is possible to generate it even at 3'. In that case, FF11
5' and FF116' are unnecessary.

In the busy check circuit 130', the NOR circuit 131
' is the machine cycle τ2 in FIG. 6 when the outputs of FFs 123' and 125' of C3RC120' are "0".
The NP1 timing check signal is generated at the NP1 timing check signal. Furthermore, FF127', FF125' and FF1 are connected to one input terminal of AND circuits 132', 133' and 134'.
The 0 outputs of FFI 23' are respectively inputted, and the Q outputs of FFI 28', FF126' and FF124' are respectively inputted to the other input terminal, and these output terminals are connected to the input terminal of NOR circuit 135'.

These AND circuits 132' to 134' and the NOR circuit 13
5', NP at 3 in the machine cycle of Fig. 6.
2. Generates a timing check signal.

(B) Operation of the second embodiment RD during read, write, and refresh of the second embodiment
, WT, RF, and NOP timing signals and each timing check operation are all the same as in the first embodiment, so a detailed explanation of the operations will be omitted.

Further, in the case of no operation, the timing check of the NOP timing signal is performed in machine cycles τ2 and τ3 in FIG. 6 using the N P 1 and NP2 timing check signals. Since the other operations are the same as those in the first embodiment during no operation, a detailed explanation of the operations will be omitted.

Although each embodiment of the present invention has been described above, each structure of the present invention is not limited to the structure of each of the above-mentioned embodiments.

For example, the C3RC 120 may be provided separately from the timing circuit 110. Further, the machine cycle in which operations such as read and write operations are performed is not limited to 2τ or 3τ.

〔Effect of the invention〕

As described above, according to the present invention, the NP timing check signal can be generated from the operation command CMD and the timing check regarding no-operation can be performed with a simple configuration. Furthermore, since the NP timing check signal can be generated from the operation command CMD, it is possible to perform a timing check at the time of no operation of a storage device, such as a memory card, to which only the operation CMD is input from the control section.

[Brief explanation of drawings]

Fig. 1: Detailed explanatory diagram of the present invention Fig. 2: Waveform diagrams of RAS, CAS, and WE in each timing signal during read, write, refresh, and no-operation, Fig. 3... An explanatory diagram of the operation commands used in the first and second embodiments of the present invention, FIG. 4... An explanatory diagram of the configuration of the first embodiment of the present invention, FIG. 5... Explanatory diagram of the configuration of the second embodiment, No. 6
Figure: RA in each timing signal of the second embodiment
In each waveform diagram of S, CAS, and WE, and FIG. 7, an explanatory diagram of a conventional timing signal check method, and FIGS. 1, 4, and 5, 110... timing circuit, 120... Command shift register circuit (C3RC), 130... Busy check circuit, 140... Timing check circuit C
MD, CMDo, CMDl - operation commands. Patent applicant: Fujitsu Ltd. -m-. Each Taimiragui 8 hanging h (hogeru RAS, CAS, WE
No. 5 Yugo Taumei Figure 2 Words of the present invention Sei Shrine 1 - Rough Raiseru Zubeshi - Scene Command CMD Figure 3 RAS, CAS, WEω thorny diagram Figure 6 Figure 7

Claims (2)

[Claims] (1) In the method of checking each timing signal for reading, writing, etc. to memory, (a) Timing for generating timing signals related to operations such as reading and writing based on operation command CMD instructing read, writing, etc. circuit(
110); (b) a command shift register circuit (120) that sequentially shifts the input operation command CMD at machine cycle timing and outputs the state of the operation command CMD at each shift stage; (c) a command shift register Signal for checking the timing signal regarding no-operation when the circuit (120) is not busy (NP timing check signal)
(d) a timing check circuit that checks timing signals related to operations such as read and write, and also checks timing signals related to no-operation when receiving the NP timing check signal; (1
40) A timing check method characterized by comprising: (2) The first claim characterized in that the command shift register circuit (120) is shared with a command shift register circuit in the timing circuit (110).
Timing check method described in section.