JPH02214094A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the deviation of the output timing of an output control signal, the output of erroneous data, and the lowering of readout speed occurring by outputting readout information from a cell held at a latch circuit based on the output control signal in which a cell selection signal is delayed for constant time. CONSTITUTION:Readout output from a memory cell 12 selected by the cell selection signal DWL is held at the latch circuit 2, and is outputted via an output circuit 3 controlled by the output control signal. The signal DWL delayed at a delay circuit 13 for the constant time is used as the output control signal, and the delay time is easily and accurately set at the constant time, which prevents the timing of the output control signal from being deviated. Thereby, a semiconductor memory without generating the output of the erroneous readout output or the lowering of the readout speed can be obtained.

Description

[Detailed Description of the Invention] [Summary] To prevent a shift in the output timing of an output control signal in a read data output circuit of a semiconductor memory device so as to prevent output of erroneous data and reduction in read speed. The purpose is to hold the cell information read from the selected cell in a latch circuit, output the holding signal of the latch circuit via the output circuit, and input the output signal of the output circuit to the same output circuit. In a semiconductor memory device that outputs an output based on an output control signal, a selection signal for selecting a cell is formed by delaying the output control signal 1 by a predetermined time using a delay circuit.

[Industrial Field of Application] The present invention relates to a read data output circuit for a semiconductor memory device.

In a semiconductor memory device such as an SRAM, cell information read out to a data bus line based on the selection of the memory cell is latched by a latch circuit, and the output signal of the latch circuit is sent to an output circuit that operates based on an output control signal. It is readable. When the cell information of a memory cell at the same address is repeatedly read, the output signal of the latch circuit is changed by continuously outputting an output control signal to the output circuit without reading the cell information of the memory cell each time. By repeatedly reading, desired cell information is read while improving the read speed.

In such a semiconductor memory device, in the case of a normal read operation in which a predetermined memory cell is selected and cell information is read out, an output control signal is output to an output circuit after the cell information is read into a latch circuit. It is necessary to read the output signal of the latch circuit.

[Prior Art] As shown in FIG. 5, in a conventional data reading device, cell information read onto a data bus line 1 is held in a latch circuit 2, and the holding signal of the latch circuit 2 is sent to an output circuit. 3
is output to. The output circuit 3 receives an output control signal O.
When EI is output and its output control signal OEI becomes H level, the holding signal of the latch circuit 2 is output as the output signal DOU of the output circuit 3.

In the signal generating circuit for forming this output control signal oE1, as shown in FIG. 6, the reference control signal OE, which is always at an L level, is outputted to one input terminal of the NOR circuit 4, as shown in FIG. A chip select signal C8 is input to the input terminal. Therefore, when the chip select signal C8 goes to the L level, the NOR circuit 4 outputs a signal at the H level, and the output signal of the NOR circuit 4 passes through the delay circuit 5, which is composed of, for example, multiple stages of inverters, to the output control signal OE1. The signal is output to the output circuit 3 as follows.

In the data reading device configured in this manner, when the chip select signal C8 is inputted as shown in FIG. 7, the relevant cell is selected, and after a predetermined time, the cell information is read out to the data bus line 1. By holding the cell information in the latch circuit 2, the holding signal L1 that was held in the latch circuit 2 up to that point is switched to the holding signal L2 corresponding to the cell information. After the holding signal of the latch circuit 2 is switched to L2, the H level output control signal OE1 is output to the output circuit 3, and the holding signal L2 of the latch circuit 2 is outputted from the output circuit 3 as the output signal DOut. .

Therefore, the delay time t1 of the delay circuit 5 of the signal generation circuit
needs to be set to a time slightly longer than the time required for the latch circuit 2 to hold the cell information of the cell as the hold signal L2 after the chip select signal C8 is input.

[Problems to be Solved by the Invention] However, in the above reading device, the output control signal OEI is formed by significantly delaying the chip select signal C8 in the delay circuit 5, so it is difficult to accurately determine the delay time t1. It becomes difficult to configure. For example, if the delay time t1 becomes short and the output control signal OEI goes to H level as shown by the chain line in FIG. The incorrect data De shown is output. Furthermore, if the output control signal OF, 1 is output to the output circuit 3 when the holding signal of the latch circuit 2 switches from Ll to L2, there is a problem that a delay occurs in the output of the output signal Dout, and the read speed decreases. There is.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that prevents the output timing shift of the output control signal from occurring, thereby preventing output of erroneous data and reduction in read speed.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, the cell information read from the selected cell 12 is held in the latch circuit 2, and the holding signal of the latch circuit 2 is outputted via the output circuit 3 and the output signal Dout of the output circuit 3. is output based on the output control signal OEI input to the output circuit 3. And output control signal OE
I is the selection signal DWL for selecting cell 12, and the delay circuit 1
3, it is formed with a certain time delay.

[Operation] Immediately after the selection signal DWL is output, the relevant cell information is held in the latch circuit 2 as a holding signal, so if the selection signal DWL is delayed by 1 in the delay circuit 13 and output to the output circuit 3. , the holding signal held in the latch circuit 2 is output from the output circuit 3.

[Embodiment] An embodiment of a data reading device embodying the present invention will be described below with reference to the drawings. The signal generating circuit shown in FIG. 2 forms the output control signal OE1 to be output to the output circuit 3. be. The configuration will be explained next. The clock signal AP input to the inverter 6a is a signal output every time an address changes during a read operation, and the output signal of the inverter 6a is output to the NAND circuit R17a via the inverter 6b. be done. Also, NAN
A write control signal WE, which is always at H level during a read operation, is input to the D circuit 7a.

The word line selection signal DWL input to the inverter 6C and the NAND circuit 7b is applied to the word line 10 for selecting the dummy cell 9 provided in the cell area 8 of this semiconductor memory device, as shown in FIG. potential is input,
The word line 10 is simultaneously selected by the row decoder 11 when any cell in the cell area 8 is selected.
It is structured as a level. And inba~
The output signal of the circuit 6c is output to the NAND circuit 7b via the inverter 6d, and the output signal of the NAND circuit 7b is output to the NAND circuit 7a.

The output signal of the NAND circuit 7a is outputted as a read signal RE to the NAND circuit 7c, and the chip select signal C8 is sent to the NAND circuit R7c via an inverter 6e.
is entered. The output signal of the NAND circuit 7c is outputted to the output diagram 113 as the output control signal OEI via the inverter 6f.

Now, in the semiconductor memory device configured in this way, the third
As shown in the figure, when the chip select signal C8 goes from 1 level to L level in order to select a predetermined cell, address change signal AC is output, and based on the address change signal AC, a clock signal of H level is output. AP is input to the inverter 6a. When the chip select signal cs is at the L level, the clock signal AP goes to the H level, and the word line selection signal DWL is at the L level, the read signal RE output from the NAND circuit 7a goes to the L level, and accordingly. Then, the output control signal OEI output from the inverter 6f becomes L level, and the output of the output signal Dout from the output circuit 3 is stopped.

In this state, when a word line selection signal is output from the row decoder 11 and a predetermined cell is selected, the row decoder 1
The word line selection signal DWL for selecting the dummy cell 9 from 1 is also output at the same time, and the cell information of the selected cell is immediately read out to the data bus line 1, and the holding signal of the latch circuit 2 is set by the cell information. Switches from Ll to L2.

Here, when the H level word line selection signal DWL is output to the inverter 6C, the output signal of the NAND circuit 7b becomes L level with a delay of the operating time of the inverters 6c and 6d, and based on the output signal, the NAND circuit The read signal RE of 7a becomes H level, and this read signal RE
Output control signal O output from inverter 6f based on
EI becomes H level. Then, the output circuit 3 outputs the holding signal L2 of the latch circuit 2 as the output signal Dout.

As described above, in this data reading device, the word line selection signal DWL is used as a reference signal for forming the output control signal OEI, and the word line selection signal DWL is high.
The output control signal OEI is output with a slight delay time t2 corresponding to the operating time of the inverters 6c, 6d, etc. while being inverted. Then, the word line selection signal D
When WL is inverted to H level, the cell information of the selected cell is immediately held in the latch circuit 2 as a new holding signal L2, and then the output control signal OEI is output and the holding signal L2 is sent to the output circuit. 3 to output signal DOLlt
is output as

Therefore, the word line selection signal D is inverted to H level immediately before the new holding signal L2 is held in the latch rgJ path 2.
Since the output control signal OE1 is formed using WL as a reference signal, the output control signal OE for the word line selection signal DWL is
The delay time t2 of I can be made small. As a result, it is possible to set an accurate delay time t2 with a small error, so that the output circuit 3 does not output erroneous data or delay the access time.

[Effects of the Invention] As detailed above, the present invention can provide a semiconductor memory device that can prevent output timing shifts of output control signals, thereby preventing output of erroneous data and reduction in read speed. Demonstrates excellent effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of this invention, and FIG. 2 is a circuit diagram showing an output control signal generation circuit of an embodiment embodying the invention.
FIG. 3 is a waveform diagram showing the operation of the data reading device according to the embodiment of the present invention, FIG. 4 is a conceptual diagram showing the configuration of the cell area for extracting the word line selection signal, and FIG. 5 is a waveform diagram showing the operation of the data reading device according to the embodiment of the present invention. FIG. 6 is a circuit diagram of a conventional output control signal generation circuit, and FIG. 7 is a waveform diagram showing its operation. In the figure, 2 is a latch circuit, 3 is an output circuit, 12 is a cell, 1
3 is a delay circuit, DWL is a selection signal, D is cell information, L is a holding signal, and 0LIt is an output signal. Conceptual diagram showing the structure of the castle Figure 5 Figure 5 Circuit diagram of data drafting device Figure 6 Conventional output control ift signal generation circuit diagram

Claims (1)

[Claims] 1. The sale information (D) read from the selected cell (12) is held in the latch circuit (2), and the holding signal (L) of the latch circuit (2) is output to the circuit. (3) and the output signal (Dout) of the output circuit (3).
) is the output control signal (OE
In the semiconductor memory device output based on 1), the output control signal (OE1) is formed by delaying the selection signal (DWL) for selecting the cell (12) by a certain period of time in the delay circuit (13). semiconductor storage device.