JPH11297075A - Semiconductor memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relaize the low power consumption of a semiconductor memory by sharply reducing the charging current of a bit line after a write operation is completed. SOLUTION: In a semiconductor memory system, a word line WL is set to an active state only for a set period while a first clock edge is used as a reference. In a write operation, after potentials of bit lines BL, BLB, as a pair, selected by a column switch 2 reach a potential required for writing data to a memory cell 101, the word line WL is set to the active state only for the set period while a second clock edge is used as a reference. Thereby, even in the write operation, amplitudes of the bit lines BL, BLB, as the pair, selected by the column switch 2 can be made extremely small. As a result, charging currents of the bit lines after the completion of the write operation can be reduced sharply, and the low power consumption of the semiconductor memory system can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
More specifically, it relates to read / write control of the device.

[0002]

2. Description of the Related Art In recent years, demands for both high-speed operation and low power consumption in semiconductor memory devices have been more and more increased. In particular, as the capacity of a static memory or cache memory mounted on a microprocessor or the like increases, reducing power consumption is an important problem.

A conventional semiconductor memory device uses a clock CLK
Is written in one cycle, and the word line is activated during the first half cycle of the clock CLK. Hereinafter, details of the conventional semiconductor memory device will be described.

FIG. 7 is a block diagram showing a configuration example of a conventional semiconductor memory device. In FIG. 7, 1 is a memory cell array, 2 is a column switch, 3 is a data input buffer, 4 is a sense circuit, 5 is a data output buffer, 6 is a word line driver, 8 is a control circuit, AD is an address signal, CLK is Is a clock input, DOUT is a data output output from the data output buffer 5, and DIN is a data input input to the data input buffer 3. Further, the memory cell array 1 has m rows and n rows, although there is no particular limitation.
An example is shown in which a matrix of columns is shown,
01 is a memory cell, WL1, WL2 to WLm are word lines, BL1, BL2 to BLn and BL1B, BL2B to B
LnB is a bit line pair. FIG. 8 shows a schematic timing waveform of a main part of the semiconductor memory device shown in FIG. 7 at the time of reading and at the time of writing.

The operation of the semiconductor memory device configured as described above will be described below.

At the time of reading, the word lines WL1 to WLm are driven by the word line driver 6 in accordance with the address signal AD, and the memory cells 101 corresponding to the selected word line are read.
Is the bit line pair BL1, BL1B to BLn, BL
nB. That is, when one word line is selected from the word lines WL1 to WLm, n memory cells 101 are simultaneously selected, and the bit line pair BL1, BL1B to BL1 is selected.
Data is output to all of n and BLnB. Then, the bit line pair BL, BLB selected by the column switch 2
Is amplified by the sense circuit 4 and output as the data output DOUT by the data output buffer 5.

On the other hand, at the time of writing, the data input DIN input to the data input buffer 3 is transmitted to the bit line pair BL, BLB selected by the column switch 2.
Then, data is written to the memory cell 101 corresponding to the word line selected by the word line driver 6.

[0008] These read / write operations are general operations of a normal static RAM.

Next, the timing will be described in detail with reference to FIG. FIG. 8 shows how the control circuit 8 controls the word line WL in two cases (a) and (b). Both reading and writing are performed in one cycle of the clock CLK. And clock C
The first half cycle of LK operates as an activation period, and the latter half cycle operates as a procharge period.

In the case (a), the word line WL is connected to the clock C
When LK is input, it is controlled by the control circuit 8 and activated with a delay in synchronization with the clock CLK. The data input DIN is determined based on the second edge of the clock CLK.

At the time of reading, data of the memory cell 101 is output to the bit line pair BL, BLB. Then, the data of the bit line pair BL, BLB selected by the column switch 2 is transmitted to the sense circuit 4. At this time, the bit line pair BL, BL not selected by the column switch 2
Data is also output to B. Since the bit line pair BL, BLB not selected by the column switch 2 is separated from the subsequent circuits by the column switch 2, the load capacity is slightly smaller than the selected bit line pair BL, BLB, and the selected bit line pair BL, BLB The amplitude is slightly larger.

At the time of writing, data corresponding to the data input DIN is transmitted from the data input buffer 3 to the bit line pair BL, BLB selected by the column switch 2. At this time, the bit line pair BL, BLB not selected by the column switch 2 is in the same state as the read state because the word line WL is in the active state, and the memory cell 101
Is output to the bit line pair.

The case (b) shows the case where the amplitude of the bit line pair BL and BLB is suppressed by making the word line WL active only for a certain period during reading. This is a technique widely used in static RAM. However, at the time of writing, since the data input DIN is determined based on the second edge of the clock CLK, the word line WL is connected to the clock C as in the case of (a).
It is activated with a delay in synchronization with LK.

In each case, the bit line pair BL, B
LB is precharged to the power supply voltage when word line WL is inactive. The precharge control is omitted and not shown in the figure.

[0015]

However, the above-described conventional configuration has a problem that power consumption is large.
That is, at the time of writing, the bit line pair BL, BLB not selected by the column switch 2 is in the same state as at the time of reading because the word line WL is in the active state, and the bit line pair BL, BLB has a large amplitude. Resulting in. For this reason, after the writing is completed, the bit line charging current for precharging all the bit lines selected by the word line WL to the power supply voltage becomes extremely large. For example, when 8: 1 selection is performed by the column switch 2, while the bit line pair BL and BLB to which data is input is one pair,
There are seven pairs of bit lines BL and BLB which are not selected by the column switch 2 and are in the same state as in the read operation. The operation of the bit line pair BL and BLB which is in the same state as at the time of reading is an unnecessary operation, and the bit line charging current corresponding thereto is a useless current, which is a major problem for reducing the power consumption of the semiconductor memory device. I have.

The present invention solves the above-mentioned conventional problems. At the time of writing, the amplitude of a bit line pair not selected by a column switch is suppressed, and the bit line charging current required after completion of writing is greatly reduced. It is an object of the present invention to provide a semiconductor memory device capable of realizing low power consumption by minimizing power consumption.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor memory device which performs a read / write operation in one clock cycle. A means is provided for activating the word line only for a predetermined period with reference to one clock edge, and for activating the word line only for a predetermined period with reference to the second clock edge during writing.

According to a second aspect of the present invention, there is provided a semiconductor memory device which is activated based on a first clock edge and precharged based on a second clock edge. Means for activating a word line only for a predetermined period by an activation pulse generated based on a clock edge, and activating the word line only for a predetermined period by an activation pulse generated based on a second clock edge during writing. It is characterized by having.

According to a third aspect of the present invention, the word line is activated by synchronizing and delaying the first clock edge, and the word line is deactivated by synchronizing and delaying the second clock edge. In the semiconductor memory device having the configuration, the word line is made inactive after a certain period from the first clock edge at the time of reading, and the word line is made inactive during the period from the first clock edge to the second clock edge at the time of writing. A means for inactivating the word line only for a predetermined period from the second clock edge by inactivating the word line is provided.

According to a fourth aspect of the present invention, in a semiconductor memory device in which a read / write operation is controlled by a first clock and a second clock whose phase is shifted, a read operation of the first clock is performed during a read operation. A word line is activated only for a certain period with reference to one edge or the first edge of the second clock, and at the time of writing, with reference to the second edge of the first clock or the second edge of the second clock. A means for activating a word line only for a predetermined period is provided.

According to a fifth aspect of the present invention, there is provided a reference clock edge for reading and a reference clock edge for determining data input at the time of writing. The reference clock edge is an externally input clock, or an edge of an internal clock generated based on an external signal.When reading, the word line is activated only for a certain period based on the read reference clock edge, At the time of writing, there is provided means for activating the word line only for a predetermined period with reference to the reference clock edge for determining the data input.

According to a sixth aspect of the present invention, there is provided a semiconductor memory device according to the first, second, third, fourth or fifth aspect.
When writing data to a memory cell, after a potential of a bit line pair selected by a column switch reaches a potential required to write the data to the memory cell, a word line to be written only for a certain period required for writing. Is provided with means for activating the.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the first, second, third, fourth, fifth or sixth aspect, the memory cells in the semiconductor memory device are constituted by a static memory cell array. The data of the memory cell selected by the word line is read out via the bit line pair, and the input data is written to the memory cell via the bit line pair selected by the column switch.

With the above configuration, in the semiconductor memory device according to the first, sixth and seventh aspects of the present invention, at the time of reading, the word line is activated only for a certain period of time with reference to the first clock edge. The data of the type memory cell is read via the bit line pair. On the other hand, at the time of writing, after the potential of the bit line pair selected by the column switch reaches the potential required to write the data to the memory cell, the word line is activated only for a certain period with reference to the second clock edge. State. Thereby, even during writing, the amplitude of the bit line pair not selected by the column switch can be suppressed, and the power consumption of the semiconductor memory device can be reduced.

According to the second aspect of the present invention, at the time of reading, the first clock edge is used as a reference, and at the time of writing, the second clock edge is used.
By activating the word line only for a certain period by using an activation pulse generated based on the clock edge of (1), the same effect as the first aspect of the present invention is achieved.

According to the third aspect of the present invention, the word line is made inactive after a certain period from the first clock edge at the time of reading, and the period from the first clock edge to the second clock edge at the time of writing. By setting the word line to the inactive state and setting the word line to the active state only for a certain period from the second clock edge, the same effect as the first aspect of the present invention is achieved.

According to the present invention, two types of clocks having different phases are used, and the first edge of the first or second clock is used as a reference for reading and the first or second clock is used for writing. By activating the word line only for a certain period of time based on the second edge of the clock, the same operation as the first aspect of the invention can be achieved.

According to the fifth aspect of the present invention, the external input clock or the internally generated clock is used, and the read operation is based on the reference clock edge for reading, and the write operation is performed for a certain period of time based on the reference clock edge for defining the data input. By setting only the word line to the active state, the same operation as the first aspect of the invention is achieved.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to a first embodiment of the present invention. FIG.
1, 1 is a memory cell array, 2 is a column switch, 3 is a data input buffer, 4 is a sense circuit, 5 is a data output buffer, 6 is a word line driver, 7 is a control circuit, AD is an address signal, and CLK is a clock. The input, DOUT, is a data output output from the data output buffer 5, and DIN is a data input, input to the data input buffer 3. Further, although there is no particular limitation, the memory cell array 1 shows an example in which the memory cell array 1 is configured in a matrix of m rows and n columns.
L2 to WLm are word lines, BL1, BL2 to BLn and B
L1B and BL2B to BLnB are bit line pairs, respectively. FIG. 2 shows a schematic timing waveform of a main part in the case of reading and writing in the semiconductor memory device shown in FIG.

In the semiconductor memory device according to the present embodiment configured as described above, the word line WL is activated for a certain period with reference to the rising edge of the clock CLK during reading, and the falling edge of the clock CLK during writing. , The word line WL is activated only for a certain period. Hereinafter, the operation will be described in detail.

The operation at the time of reading and writing is the same as the general operation of the ordinary static RAM shown in the conventional example.

The word line WL is controlled by a control circuit 7 to which a clock CLK and a write control signal WE are inputted. The control circuit 7 includes a read-time pulse generation circuit and a write-time pulse generation circuit. The control circuit 7 generates different pulses at the time of reading and at the time of writing, and controls the word line WL. At the time of reading, the word line is controlled so as to be in an active state only for a certain period based on the first edge of the clock CLK. On the other hand, at the time of writing, the data input DIN is determined based on the second edge of the clock CLK, and the word line WL is controlled to be active only for a certain period of time based on the second edge of the clock CLK.

A more detailed schematic timing waveform of a main part at the time of reading and writing will be described in detail with reference to FIG.

In FIG. 2, at the time of reading, the word line W
L is activated only for a certain period by an activation pulse generated based on the first edge of the clock CLK. This is because a method of detecting a transition of an address often used in a static RAM and generating a pulse is a clock CL.
This can be realized by using the first edge of K or the like. On the other hand, during writing, the data input DIN is applied to the clock CLK.
Is determined based on the second edge of the clock CLK
No activation pulse is generated based on the first edge of the clock signal CLK, and an activation pulse is generated based on the second edge of the clock CLK to activate the word line WL only for a certain period. This method also employs a method of detecting a transition of an address often used in a static RAM and generating a pulse by using a clock C.
It can be realized by using the second edge of LK.

As in the conventional example, the bit line pair BL, B
LB is precharged to the power supply voltage when the word line WL is in an inactive state, but the precharge control is not shown in the drawing and the description is omitted.

The decrease in the amplitude of the bit line pair BL and BLB at the time of reading is the same as that of the conventional example shown in FIG. On the other hand, at the time of writing, data corresponding to the data input DIN is transmitted by the data input buffer 3 to the bit line pair BL, BLB selected by the column switch 2. However, since word line WL is still inactive, memory cell 1
No data is written in 01, and the bit line pair BL, BLB not selected by the column switch 2 does not swing in the precharged state. Thereafter, when the data input DIN is determined and the word line WL is activated only for a certain period with reference to the second edge of the clock CLK, the bit line pair BL, BLB selected by the column switch 2
Is already written to the memory cell 101. At this time, the bit line pairs BL and BLB not selected by the column switch 2 are in the read state,
Since the active period of the word line WL is short, the amplitude is extremely small. Then, it immediately returns to the precharge state.

FIG. 3 is a diagram showing schematic waveforms at the time of reading and writing when the control circuit 7 controls the word line WL differently from the first embodiment of the present invention shown in FIG.

In the embodiment shown in FIG. 2, an activation pulse is generated based on the second edge of the clock CLK at the time of writing, so that the word line WL has the clock CLK which is originally a precharge period. L (low) ", the active state is activated, the timing at which the word line WL returns to the non-selected state after writing is delayed, and the subsequent bit line pair BL, B
The time required for pre-charging LB becomes shorter,
There is a possibility that the operation in the next cycle may not be completed.

In the embodiment shown in FIG. 3, the word line WL has a delay (indicated by a broken line) in synchronization with the clock CLK, and at the time of reading, after a fixed period from the first edge of the clock CLK. The word line WL is made inactive, while at the time of writing, the word line WL is made inactive for a period from the first edge to the second edge of the clock CLK, and the word line WL is kept for a certain period from the second edge of the clock CLK. Control is performed by the control circuit 7 so that WL is activated.

As a result, in the embodiment shown in FIG.
The timing at which the word line WL returns to the non-selected state after writing is earlier than in the case of the embodiment shown in FIG. 2, and sufficient precharge can be performed by the next cycle. FIG. 2 shows that the amplitude of the bit line pair BL, BLB not selected by the column switch 2 at the time of writing can be made extremely small.
This is the same as the embodiment shown in FIG.

FIG. 4 is a diagram showing an example of a read pulse generator and a write pulse generator in the waveform generation control circuit 7 for controlling the word line WL as shown in FIG. is there.

In this circuit, depending on the state of the clock CLK and the write control signal WE, at the time of reading as shown in FIG. 3, the word line WL becomes inactive after a certain period from the first edge of the clock CLK, and At this time, a control signal for inactivating the word line WL during a period from the first edge to the second edge of the clock CLK and activating the word line WL only for a certain period from the second edge of the clock CLK is issued. Occur.

As described above, according to the semiconductor memory device of the present embodiment, at the time of reading, the word line WL is activated only for a certain period with reference to the first clock edge. On the other hand, at the time of writing, after the potential of the pair of bit lines BL and BLB selected by the column switch 2 reaches a potential necessary for writing data to the memory cell 101, the word is written only for a certain period with reference to the second clock edge. The line WL is activated. Thus, even at the time of writing, the amplitude of the bit line pair BL, BLB not selected by the column switch 2 can be extremely reduced. Therefore, the bit line charging current after writing is completed can be greatly reduced,
Low power consumption of the semiconductor memory device can be realized.

FIG. 5 is a diagram showing schematic waveforms at the time of reading and writing of the semiconductor memory device according to the second embodiment of the present invention.

In FIG. 5, the clock inputs are clocks 1CLK1 and 2CLK having different phases and duty ratios (ratio of "H (high)" and "L (low)" periods of the clock).
2, there are two clock inputs, clock 1CLK1,
The operation and its effects are exactly the same as those of the first embodiment shown in FIGS. 1 to 4 except that the activation period of the word line WL is controlled using both clock edges of the clock 2CLK2. It is.

FIG. 6 is a diagram showing schematic waveforms at the time of reading and writing of the semiconductor memory device according to the third embodiment of the present invention.

In FIG. 6, a clock CLK is a control clock input from the outside or an internal clock generated by a method of detecting a transition of the address signal AD with reference to an external signal. In this figure, the read reference clock edge is at timing t1r
And the reference clock edge for determining the data input DIN at the time of writing is timing t2w. When reading,
The word line WL is activated only for a certain period with reference to the read reference clock edge (t1r). On the other hand, at the time of writing, the reference clock edge for confirming the data input (t2w)
, The word line WL is activated only for a certain period.
Except that the reference clock edge is different, the operation and its effects are exactly the same as those of the first embodiment shown in FIGS.

The control method and control circuit of the activation period of the word line WL are not limited to those shown in FIGS.

[0050]

As described above, according to the semiconductor memory device of the present invention, at the time of reading, the word line is activated only for a certain period with reference to the first clock edge, while at the time of writing, the column switch is activated. After the potential of the selected bit line pair reaches the potential required to write the data in the memory cell, the word line is activated only for a certain period with reference to the second clock edge. Thus, even at the time of writing, the amplitude of the bit line pair not selected by the column switch can be made extremely small. As a result, the bit line charging current after writing is completed can be significantly reduced, and low power consumption of the semiconductor memory device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a schematic waveform at the time of reading and writing of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a diagram showing a schematic waveform at the time of reading and writing in the case of control different from that of FIG. 2;

FIG. 4 is a diagram showing an example of a control circuit for generating the waveform shown in FIG.

FIG. 5 is a view showing a schematic waveform at the time of reading and writing of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 6 is a diagram showing a schematic waveform at the time of reading and writing in the semiconductor memory device according to the third embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration example of a conventional semiconductor memory device;

FIG. 8 is a diagram showing a schematic waveform at the time of reading and writing of a conventional semiconductor memory device;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Column switch 3 Data input buffer 4 Sense circuit 5 Data output buffer 6 Word line driver 7 Control circuit 8 Control circuit 101 Memory cell

Claims (7)

[Claims] 1. A semiconductor memory device that executes a read / write operation in one cycle of a clock, wherein a word line is activated only for a certain period with reference to a first clock edge during a read operation, and the first clock is applied during a write operation. A semiconductor memory device comprising: means for activating the word line only for a certain period of time based on a second clock edge having a different timing from an edge. 2. A semiconductor memory device which is activated based on a first clock edge and is precharged based on a second clock edge having a different timing from the first clock edge. The word line is activated only for a predetermined period by an activation pulse generated based on the first clock edge, and the word line is activated only for a predetermined period by an activation pulse generated based on the second clock edge during writing. A semiconductor memory device comprising: means for activating the semiconductor memory device. 3. A word line is activated by synchronizing and delaying with a first clock edge, and deactivating a word line by synchronizing and delaying with a second clock edge different in timing from the first clock edge. In a semiconductor memory device configured to be in a state, a word line is made inactive after a predetermined period from the first clock edge during reading, and a period from the first clock edge to the second clock edge during writing. A semiconductor memory device comprising means for inactivating the word line to activate the word line only for a predetermined period from the second clock edge. 4. A semiconductor memory device in which a read / write operation is controlled by a first clock and a second clock having a phase shift, wherein a first edge of the first clock or a second clock is read at the time of reading. , The word line is activated only for a certain period based on the first edge of the word line, and at the time of writing, the word line is activated only for a certain period based on the second edge of the first clock or the second edge of the second clock. A semiconductor memory device comprising: 5. A reference clock edge for reading and a reference clock edge for defining data input at the time of writing, wherein the reference clock edge for reading and the reference clock edge for defining data at the time of writing are externally input. Clock, or an edge of an internal clock generated on the basis of an external signal. In a read operation, the word line is activated only for a certain period of time based on the read reference clock edge, and in a write operation, the data input is determined. A semiconductor memory device comprising: means for activating the word line only for a predetermined period with reference to a reference clock edge. 6. When writing data to a memory cell, after a potential of a bit line pair selected by a column switch reaches a potential required for writing the data to the memory cell, only for a predetermined period required for writing. 6. The semiconductor memory device according to claim 1, further comprising means for activating a word line to be written. 7. The memory cell includes a static memory cell, reads data of a memory cell selected by a word line via a bit line pair, and reads input data of the bit line selected by the column switch. 7. The semiconductor memory device according to claim 1, wherein data is written to said memory cell via a pair.