JPS62128671U - - Google Patents
Info
- Publication number
- JPS62128671U JPS62128671U JP1628286U JP1628286U JPS62128671U JP S62128671 U JPS62128671 U JP S62128671U JP 1628286 U JP1628286 U JP 1628286U JP 1628286 U JP1628286 U JP 1628286U JP S62128671 U JPS62128671 U JP S62128671U
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- solder
- component mounting
- dummy pattern
- mounting board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000006071 cream Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Description
第１図ａ、第１図ｂ、第１図ｃ、第１図ｄ、第
１図ｅ、は本考案の一実施例の電子部品取付け工
程を説明するための一部断面図、第２図は半田ボ
ールとレジスト厚みとの関係を示す説明図、第３
図ａ、第３図ｂ、第３図ｃ、第３図ｄは従来例の
電子部品取付け工程を説明するための一部断面図
、第４図は従来例の半田ボール発生時の状態を示
す斜視図である。
１……取付け基板、２ａ，２ｂ……半田ランド
、３……レジスト、４……クリーム半田、５……
チツプ電子部品、６ａ，６ｂ……電極、１０……
ダミーパターン。
1a, 1b, 1c, 1d, and 1e are partial cross-sectional views for explaining the electronic component mounting process according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing the relationship between solder balls and resist thickness.
Figure a, Figure 3b, Figure 3c, and Figure 3d are partial cross-sectional views for explaining the electronic component mounting process of the conventional example, and Figure 4 shows the state when solder balls occur in the conventional example. FIG. 1...Mounting board, 2a, 2b...Solder land, 3...Resist, 4...Cream solder, 5...
Chip electronic components, 6a, 6b...electrodes, 10...
dummy pattern.
Claims (1)
ーム半田を設け、このクリーム半田を介してチツ
プ電子部品を前記半田ランド間に固定する電子部
品取付け基板において、前記半田ランド間にダミ
ーパターンを隆起形成し、このダミーパターンの
上にレジストを施すことを特徴とした電子部品取
付け基板。 In an electronic component mounting board in which cream solder is provided on a pair of solder lands formed on one side, and a chip electronic component is fixed between the solder lands via the cream solder, a dummy pattern is formed as a protrusion between the solder lands. This electronic component mounting board is characterized by applying a resist on top of this dummy pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1628286U JPS62128671U (en) | 1986-02-08 | 1986-02-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1628286U JPS62128671U (en) | 1986-02-08 | 1986-02-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62128671U true JPS62128671U (en) | 1987-08-14 |
Family
ID=30807997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1628286U Pending JPS62128671U (en) | 1986-02-08 | 1986-02-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62128671U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593294A (en) * | 1979-01-05 | 1980-07-15 | Matsushita Electric Ind Co Ltd | Reflow soldering method |
| JPS5678190A (en) * | 1979-11-30 | 1981-06-26 | Matsushita Electric Works Ltd | Electric circuit block |
-
1986
- 1986-02-08 JP JP1628286U patent/JPS62128671U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593294A (en) * | 1979-01-05 | 1980-07-15 | Matsushita Electric Ind Co Ltd | Reflow soldering method |
| JPS5678190A (en) * | 1979-11-30 | 1981-06-26 | Matsushita Electric Works Ltd | Electric circuit block |