JPS62128543A - Master slice system semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize the size of cells occupying on a bulk according to logics, and to improve efficiency on the use of semiconductor elements by arranging fundamental units constituted of the semiconductor elements in minimum number or less required for logical constitution having a minimum function to the bulk in an array manner. CONSTITUTION:Logics are realized in a region surrounded by a solid line in a layout conceptual figure for an LSI actualized by a system, in which fundamental units 10 are connected, and the region functions as a section as a cell region, and broken lines represent the boundaries of the fundamental units 10. Gnm is realized on a No.N array, and shows a No.m logic cell from the left on the array. Since said logic cells take different size occupying on a bulk in response to logical functions, the number of the logic cells differs at every array even when the arrays are all used. Accordingly, the size of the logic cells occupying on the bulk can be minimized according to the logics, thus improving efficiency on the use of elements, then preventing the deterioration of speed performance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a master slice type large-scale integrated circuit (LS) constructed of current switching type logic circuits, and particularly relates to a cell configuration suitable for high integration. It is about law.

[Conventional technology]

Master slice type gate arrays or macro cell arrays are widely used to improve performance and shorten development time by implementing LSI systems. A master slice type gate array or macro cell array has a bulk in which a large number of basic cells whose patterns have been designed in advance are arranged in an array, and wiring cells are placed on each of the basic cells, and between the wiring cells. By using a computer to automatically design the wiring layers that connect the LSIs, it is possible to construct a wide variety of products from a single bulk.

FIG. 6 shows a general layout of the above LSI. In the figure, 1 is an internal cell, 2 is an internal area consisting of an array of internal cells 1 and an inter-cell wiring area for mutually automatically wiring the internal cells 1, and constitutes a logic circuit, and 3 is an internal area 2. 4 is an input/output cell area consisting of the cell for the output cover sofa, 5 is a signal and power supply pad, 6 is a cell for an input/output cover sofa, which is provided outside the cell and serves as an electrical interface between the internal cell 1 and the outside of the LSI. A pad region 6 is formed by the pad/node 5, and the LSI is divided into the above regions of 2.4°6.

The internal cell 1 is composed of circuit elements such as transistors, diodes, and resistors, and a logic circuit can be realized by connecting these elements within the cell.

The element arrangement is determined by the circuit configuration for realizing logic and the type of logic desired to be realized on the cell 1.

In addition, current-switching logic circuits have high operating speeds, so
It is widely used in systems that require high-speed performance, but because it requires a relatively large number of elements, it is necessary to fabricate a large number of elements in advance in cells that can configure many types of multifunctional logic. There is a need. For example, in order to be able to configure a D latch within one cell, it is necessary to prepare as many elements in one cell as there are elements built into the cell shown in FIG.

[Problem that the invention seeks to solve]

The cells of conventional master slice type semiconductor integrated circuit devices are configured as described above, so when configuring small-function logic that does not require too many elements, many unused elements remain within the cell. Another problem is that even though the function is small, it occupies the same cell area as other logic in the bulk, which reduces the function per unit area of the LSI and also causes a decrease in speed performance. was there.

This invention was made to solve the above-mentioned problems, and it is a master slice that can minimize the cell size occupied on the bulk according to the various logics to be realized, and has high element usage efficiency through high integration. The objective is to obtain a semiconductor integrated circuit device based on this method.

Means for Solving Problem C] The master slice type semiconductor integrated circuit device according to the present invention is a basic unit composed of semiconductor elements whose number is less than the minimum number required for a logic configuration with the minimum function among desired logics. are arranged in an array in the bulk, and a plurality of the semiconductor elements of the above basic units are interconnected to realize a desired logic.

[Effect]

In this invention, since basic units composed of semiconductor elements smaller than the minimum number required for a logic configuration with the minimum function among desired logics are arranged in an array in the bulk, cells occupying the bulk in accordance with the logic are arranged in an array. The size can be minimized and the efficiency of device usage can be increased.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a master slice LSI according to an embodiment of the present invention.
In the figure, 10 is a basic unit on the bulk, and 2 is an internal region. The other parts are the same as the conventional example shown in FIG. 6, and will therefore be omitted.

Furthermore, Fig. 2 shows the basic unit 1o in Fig. 1, which is composed of three transistors and four resistors, and the number of elements is the minimum required for the logic with the minimum function among the desired logic. It is less than the number. The master slice type LSI of this embodiment has the basic unit 1 shown in FIG.
It has a structure in which a plurality of 0's are consecutively arranged in an array.

Next, a case will be described in which a specific logic circuit is constructed using the basic unit 10.

When implementing logic using an emitter-coupled logic circuit equipped with a constant current ratio circuit, how many liters does one basic unit need as shown in Figure 2?
;Cannot construct logic. Therefore, even when configuring an inverter or a simple buffer, at least two basic units 1
Requires 0. In addition, regarding the logic of two people and the logic with more functions, the basic units io; fc,
The above logic is realized by connecting a plurality of the minimum number of devices.

The one shown in Figure 3 is one of the most commonly used types of logic based on current switching type logic circuits.
This is an example of configuring R/NOR.

This can be achieved by connecting two basic units 10, and there are no unused transistors. Further, in this case, since seven resistance elements are required, the optimum number of resistances in the basic unit 10 is four. Note 5 or 6
In the case of a circuit configuration requiring 10 resistors, the basic unit is 10
The optimum number of resistors in the range is 3.

Furthermore, as an example of logic with a relatively large function, what is shown in FIG. 4 is an example in which a full adder with NOR gates having 11 equivalent gates is constructed by a two-stage series gate circuit. As is clear from the figure, this can be realized using seven resistance elements and only one unused transistor. In addition, in FIGS. 3 and 4, Vcc, VE,
v'r bottom is the 1st. Second and third power supply potentials, V
.

81, VBB2 are the first and second reference potentials, V
O2 is a bias potential for the constant current circuit.

By appropriately setting the resistance value within the basic unit, V
IE and VTT can be made common.

FIG. 5 shows a conceptual diagram of the layout of an LSI realized by the method of connecting the basic units 1o as described above. The area surrounded by solid lines is the part where logic is realized and becomes the cell area, and the broken line is the basic unit. This indicates the 1° boundary. G
nm is realized on the Nth array and indicates the mth logic cell from the left on that array.The logic cell occupies a different size on the bulk depending on the logic function, so the entire array was used. Even in this case, the number of logic cells will be different for each array.

As described above, in this embodiment, the size of the logic cell occupying the bulk can be minimized according to the logic, the efficiency of element usage can be increased, and a decrease in speed performance can be prevented.

Note that in the above embodiment, the basic unit of the internal area is composed of three transistors and four resistors, but
This basic unit may be composed of fewer than the minimum number of elements required for a logic configuration with the minimum function of the desired logic.

〔Effect of the invention〕

As described above, according to the present invention, logic can be realized by connecting a plurality of basic units each consisting of less than the minimum number of elements required for the logic configuration.
The cell size occupied on the bulk can be minimized according to the logic, which has the effect of increasing element usage efficiency and preventing deterioration in speed performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a master slice type LSI according to an embodiment of the present invention, FIG. 2 is a diagram showing a basic unit area of this invention, and FIGS. FIG. 5 is a conceptual diagram of an LSI layout realized by the present invention, and FIGS. 6 and 7 are a diagram of a conventional general master slice type LSI and an example of its internal cell area, respectively. FIG. DESCRIPTION OF SYMBOLS 1... Internal cell, 2... Internal area, 3... Human output buffer cell, 4... Input/output cell area, 5... Pad, 6... Bad area, 10... Basic unit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Ken Hayase - Figure 1 Figure 5 Figure 6 Figure 7 Procedural amendment (voluntary) February 9, 1988 To the Commissioner of the Japan Patent Office 11. Indication of the case Patent Application No. 1983-269824 2 Invention Name Master Slice Semiconductor Integrated Circuit Device 3, Person making the amendment 5, Detailed description of the invention in the specification to be amended, and drawings (Figure 1) 6. Contents of the amendment (11 Specification, page 6) “Current limit” on line 13 is “current source”
Correct. (2) [N0R with equivalent number of gates 11] on page 7, line 13
Correct J to rNORJ. (3) Figure 1 is corrected as shown in the attached sheet. that's all

Claims (2)

[Claims] (1) A master in which a plurality of basic units each having a plurality of semiconductor elements that are not connected to each other is formed, and the semiconductor elements in the plurality of basic units are arbitrarily connected to form a current switching type logic circuit. In a slicing semiconductor integrated circuit device, the basic unit is composed of less than the minimum number of semiconductor elements required to configure the logic of the minimum function, and the semiconductor elements in the plurality of basic units are interconnected. A master slice type semiconductor integrated circuit device characterized in that it is connected to realize a desired logic. (2) The current switching type logic circuit is an emitter-coupled logic circuit equipped with a constant current source circuit consisting of one transistor and one resistance element, and the basic unit is three transistors and three or four
2. The master slice type semiconductor integrated circuit device according to claim 1, wherein the master slice type semiconductor integrated circuit device is made up of a plurality of resistive elements.