JPS621238A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS621238A JPS621238A JP60139579A JP13957985A JPS621238A JP S621238 A JPS621238 A JP S621238A JP 60139579 A JP60139579 A JP 60139579A JP 13957985 A JP13957985 A JP 13957985A JP S621238 A JPS621238 A JP S621238A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- chip
- wires
- semiconductor device
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体素子と外部リー
ドとをボンディングワイヤで接続した多ビシ半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a multi-layer semiconductor device in which a semiconductor element and an external lead are connected by bonding wires.
近年のＩＣ，ＬＳＩ等の半導体装置の高密度化、高集積
化に伴って、半導体装置も多ピン化の傾向が顕著になり
、現在では２００ピン以上のＬＳＩも提案されている０
通常、この種の半導体装置では半導体素子と、これを封
止するパッケージに設けた外部リードとを電気的に接続
するために、半導体素子上に形成したボンディングパッ
ドと、外 ゛部リードのボンディング部とを極めて
細い金属線、つまりボンディングワイヤで接続している
。 例えば、第３図に示すように、半導体チップｌに配
設した複数個のボンディングパッド２ａ〜２ｈと、複数
の外部リード３ａ〜３ｈの各内部側の端部に設けたボン
ディング部４ａ〜４ｈとの間に夫々ボンディングワイヤ
５ａ〜５ｈを張設して両者の電気的接続をおこなってい
る。In recent years, with the increase in density and integration of semiconductor devices such as ICs and LSIs, there has been a noticeable trend toward increased pin counts in semiconductor devices, and LSIs with more than 200 pins are currently being proposed.
Normally, in this type of semiconductor device, in order to electrically connect the semiconductor element and the external leads provided on the package that seals it, there are bonding pads formed on the semiconductor element and bonding parts of the external leads. These are connected using extremely thin metal wires, that is, bonding wires. For example, as shown in FIG. 3, a plurality of bonding pads 2a to 2h provided on a semiconductor chip l, and bonding portions 4a to 4h provided at the inner ends of each of a plurality of external leads 3a to 3h. Bonding wires 5a to 5h are respectively stretched between them to electrically connect them.
上述した複数のボンディングパッド２ａ〜２ｈやボンデ
ィング部４ａ〜４ｈを有する半導体装置では、各ボンデ
ィングパッド２ａ〜２ｈは等しいピッチｄで配設してい
るものの、半導体チップ１とパッケージとの寸法の相違
により、ボンディングパッドとボンディング部とのピン
チ寸法は等しくないため、例えば、パッド２ａ〜２ｅと
ボンディング部４ａ〜４ｅとの間に張設されるボンディ
ングワイヤ５ａ〜５ｅでは、これらワイヤが半導体チッ
プ辺に対してなす角度θａ〜θｅはチップｌのコーナ部
へゆく程小さくなり、したがって各ボンディングワイヤ
５ａ〜５０間の間隔寸法り。In the semiconductor device having a plurality of bonding pads 2a to 2h and bonding portions 4a to 4h described above, each bonding pad 2a to 2h is arranged at the same pitch d, but due to the difference in dimensions between the semiconductor chip 1 and the package. Since the pinch dimensions of the bonding pads and the bonding parts are not equal, for example, in the bonding wires 5a to 5e stretched between the pads 2a to 2e and the bonding parts 4a to 4e, these wires are The angles θa to θe become smaller toward the corners of the chip 1, and therefore, the distance between the bonding wires 5a to 50 is the same.
〜Ｌ３もこれに伴って次第に小さくなる（Ｌ、〉Ｌ、＞
Ｌ、＞Ｌ３ ）。〜L3 also gradually becomes smaller (L,〉L,＞
L, >L3).
このため、チップｌのコーナ部では隣接するボンディン
グワイヤ同士が接触し易くなり、半導体装置の不良を生
じて組み立て歩留が低下される。Therefore, adjacent bonding wires tend to come into contact with each other at the corner portions of the chip 1, resulting in defects in the semiconductor device and a decrease in assembly yield.
特に、多ピン化された半導体装置では、チップ上に配設
するボンディングパッドの数が多いためパッド間隔も必
然的に小さくなり、ボンディングワイヤが接触される頻
度は高いものになる。In particular, in a semiconductor device with a large number of pins, the number of bonding pads disposed on a chip is large, so the spacing between the pads inevitably becomes small, and the frequency with which bonding wires are contacted becomes high.
本発明の半導体装置は、ボンディングパッドのいずれの
位置においてもボンディングワイヤ同士が接触すること
のないように、外部リードのボンディング部とボンディ
ングパッドとの間に接続するボンディングワイヤがチッ
プ辺となす角度に基ずき、チップ上に配列される複数個
のボンディングパッドの相互間の間隔寸法を前記角度の
正弦の逆数に比例するように設定している。In the semiconductor device of the present invention, the bonding wire connected between the bonding part of the external lead and the bonding pad is adjusted at an angle with the chip side so that the bonding wires do not come into contact with each other at any position of the bonding pad. Basically, the distance between a plurality of bonding pads arranged on a chip is set to be proportional to the reciprocal of the sine of the angle.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の半導体装置の一部、特に半導体チップ
１１の第１象限に相当する部分を示したものであ“る０
図において、１２ａ＝１２ｈは半導体チップｌｌ上に配
設したボンディングパッド、１３ａ〜１３ｈは図外のパ
ッケージに配設した外部リードであり、この各外部リー
ドの内端部に夫々ボンディング部１４ａ〜１４ｈを設け
ている。FIG. 1 shows a part of the semiconductor device of the present invention, particularly a part corresponding to the first quadrant of the semiconductor chip 11.
In the figure, 12a=12h are bonding pads disposed on the semiconductor chip 11, 13a to 13h are external leads disposed on a package (not shown), and bonding portions 14a to 14h are provided at the inner end of each external lead, respectively. has been established.
そして、ここでは、前記ボンディングパッド１２ａ〜１
２ｅと、ボンディング１４ａ〜１４ｅの各中心位置の間
に亘って夫々ボンディングワイヤ１５ａ〜１５ｅを接続
するものとする。更に、各外部リード１３ａ〜１３ｅの
ピッチ寸法、即ち各ボンディング部１４ａ〜１４ｅのピ
ッチ寸法は等しく設定しており、また各ボンディングワ
イヤ１５ａ〜１５ｅがチップ１１の辺となす角度を夫々
θａ〜θｅとし、本例ではボンディングパッド１２ａと
ボンディング部１４ａとを接続するボンディングワイヤ
１５ａの角度θａを９０度（直角）に設定しているもの
とする。Here, the bonding pads 12a-1
Bonding wires 15a to 15e are connected between the wire 2e and the center positions of the bondings 14a to 14e, respectively. Further, the pitch dimensions of the external leads 13a to 13e, that is, the pitch dimensions of the bonding parts 14a to 14e, are set equal, and the angles that the bonding wires 15a to 15e make with the sides of the chip 11 are set to θa to θe, respectively. In this example, it is assumed that the angle θa of the bonding wire 15a connecting the bonding pad 12a and the bonding portion 14a is set to 90 degrees (right angle).
このような条件において、本発明では各ボンディングパ
ッド１２ａ〜１２ｅ間の中心距離ｄｏｔｄ、、ｄ、、ｄ
、が夫々ｄｏ ＝Ｌａ ／ｓｉｎθａ。Under such conditions, in the present invention, the center distances dotd, d, d between each bonding pad 12a to 12e are
, respectively do = La /sinθa.
ｄ １ ＝Ｌ １ ／ Ｓｉｎθｂ＋ｄｔ ＝Ｌｔ ／
ｓｉｎθｃ、ｄ３＝Ｌ＊／ｓｉｎ θｄとなるように各
ボンディングパッド位置を設定している。ここでＬ０〜
Ｌ、は各ボンディングワイヤ１５ａ〜１５ｅ間の間隔寸
法であり、本例では各Ｌ０〜Ｌ、は全て等しく、しかも
隣接するボンディングワイヤ間の接触を防止するために
必要とされる最小の寸法となるように設定している。d 1 = L 1 / Sinθb+dt = Lt /
Each bonding pad position is set so that sin θc, d3=L*/sin θd. Here L0~
L is the spacing dimension between each bonding wire 15a to 15e, and in this example, L0 to L are all equal and are the minimum dimension required to prevent contact between adjacent bonding wires. It is set as follows.
したがって、この場合ではθａ〜θｅはチップ１１のコ
ーナ部に近づくに従って徐々に小さくなるため、各ボン
ディングパッドの間隔は、ｄ、＜ｄ、＜ｄ、＜ａｍの関
係になり、チップのコーナ部に近ずくのに伴ってパッド
間隔は徐々に大きくされている。Therefore, in this case, θa to θe gradually become smaller as they approach the corner of the chip 11, so the spacing between each bonding pad becomes d, < d, < d, < am. The spacing between the pads is gradually increased as the distance approaches.
このように構成した半導体装置では、ボンディングパッ
ド１２ａ〜１２ｅとボンディング部１４ａ〜１４ｅとを
夫々接続するボンディングワイヤ１５ａＮ１５ｅの間隔
がいずれの箇所においても等しくなり、チップのコーナ
部において低減されることはない、このため、特にチッ
プのコーナに近い箇所においても、隣接するボンディン
グワイヤ同士が接触するような傾向もなく、全てのボン
ディングワイヤにおける接触を効果的に防止上き、半導
体装置の信頼性を高めるとともに、組み立て歩留を向上
できる。In the semiconductor device configured in this manner, the distance between the bonding wires 15aN15e connecting the bonding pads 12a to 12e and the bonding parts 14a to 14e, respectively, is equal at all locations, and is not reduced at the corner portions of the chip. Therefore, there is no tendency for adjacent bonding wires to come into contact with each other, especially in locations near the corners of the chip, which effectively prevents contact between all bonding wires and improves the reliability of the semiconductor device. , the assembly yield can be improved.
第２図は本発明の他の実施例を示し、外部リ一ド２３ａ
〜２３ｅが異なるピッチ寸法で配設しである場合を示し
ている。この場合では、ボンディング部２４ａ〜２４ｅ
とボンディングパッド２２８〜２２ｅ間に接続されるボ
ンディングワイヤ２５ａ〜２５ｅがチップ２１の辺とな
す角度θａ〜θｅは必ずしもこの順序で小さくはならな
いが、この場合でも各ボンディングパッド２２ａ〜２２
８間の間隔ｄ、〜ｄ、を前述と同様にθａ〜θｅに基ず
いて各ボンディングワイヤ２５ａ〜２５ｅの間隔Ｌ０〜
Ｌ３が等しくなるように設定すればよい、この場合には
、ボンディング部２４ａ〜２４ｅの配設位置に応じてボ
ンディングパッド２２８〜２２ｅ間の間隔は不規則な寸
法になる。FIG. 2 shows another embodiment of the present invention, in which the external lead 23a
23e are arranged with different pitch dimensions. In this case, bonding parts 24a to 24e
The angles θa to θe that the bonding wires 25a to 25e connected between the bonding pads 228 to 22e and the sides of the chip 21 do not necessarily become smaller in this order;
Similarly to the above, the intervals d and ~d between the bonding wires 25a to 25e are determined based on θa to θe.
L3 may be set to be equal. In this case, the intervals between the bonding pads 228 to 22e will be irregular depending on the placement positions of the bonding portions 24a to 24e.
本実施例にあっても、各ボンディングワイヤ２５ａ〜２
５ｅの間隔Ｌ０〜Ｌ３を必要最小の寸法以上に保持する
ことにより、チップのコーナ部に限らずいずれの箇所に
おいても隣接する各ボンディングワイヤ同士の接触を有
効に防止でき、組み立て歩留を向上できる。Even in this embodiment, each bonding wire 25a to 2
By maintaining the intervals L0 to L3 of 5e to be at least the minimum required size, it is possible to effectively prevent adjacent bonding wires from coming into contact with each other not only at the corner portions of the chip but also at any location, thereby improving the assembly yield. .
ここで、ボンディングワイヤをボンディング部やボンデ
ィングパッドの中心から外れた位置に接続する場合にも
ボンディングワイヤの角度θを用いてボンディングパッ
ドの間隔寸法ｄを設定することができる。但し、この場
合には角度θに基ずいて得られた間隔寸法ｄはボンディ
ングワイヤの接続箇所を基準に計る必要がある。また、
このようなボンディングパッドの配置はチップの他の象
限においても全く同様に適用できる。Here, even when the bonding wire is connected to a position away from the center of the bonding portion or the bonding pad, the distance d between the bonding pads can be set using the angle θ of the bonding wire. However, in this case, the interval dimension d obtained based on the angle θ needs to be measured based on the connection point of the bonding wire. Also,
This arrangement of bonding pads is equally applicable to other quadrants of the chip.
以上説明したように本発明は、外部リードのボンディン
グ部とボンディングパッドとの間に接続するボンディン
グワイヤがチップ辺となす角度に基ずき、チップ上に配
列される複数個のボンディングパッドの相互間の間隔寸
法を、前記角度の正弦の逆数に比例するように設定して
いるので、ボンディングパッドの配設位置にかかわらず
ボンディングワイヤの相互間隔を略等しく保持すること
ができ、これによりいずれの箇所のボンディングワイヤ
にあっても隣接するワイヤ同士の接触を有効に防止でき
、半導体装置の信頼性を高めるとともに組み立て歩留を
向上できる。。本発明は外部リード数の多い他ピン型の
半導体装置に適用すれば、その効果は特に大きなものと
なる。As explained above, the present invention provides a method for connecting a plurality of bonding pads arranged on a chip based on the angle that the bonding wire connected between the bonding part of the external lead and the bonding pad makes with the chip side. Since the spacing dimension of is set to be proportional to the reciprocal of the sine of the above-mentioned angle, the mutual spacing between the bonding wires can be maintained approximately equal regardless of the placement position of the bonding pad. Contact between adjacent wires can be effectively prevented even in the case of bonding wires of 1 to 3, thereby increasing the reliability of the semiconductor device and improving the assembly yield. . If the present invention is applied to a multi-pin type semiconductor device with a large number of external leads, its effects will be particularly great.
第１図は本発明の半導体装置の一実施例の一部平面図、
第２図は他の実施例の一部平面図、第３図は従来構造の
一部平面図である。
１．１１．２１−・・半導体チップ、２ａ〜２ｈ、１２
ａ〜１２ｈ、２２ａ〜２２６・・・ボンディングパッド
、３ａ 〜３ｈ、 １３ａ 〜１３ｈ、２３ａ 〜２
３ ｅ ・・−外部リード、４ａ〜４ｈ、 １４ａ
〜１４ｈ。
２４ａ〜２４１３・・・ボンディング部、５ａ〜５ｈ。
１５ａ〜１５ｅ、２５ａ〜２５ｅ・・・ボンディングワ
イヤ、θａ〜θｅ・・・ボンディングワイヤのなす角度
、ｄ０〜ｄ３・・・ボンディングパッドの間隔寸法、Ｌ
、〜Ｌ、・・・ボンディングワイヤの間隔寸法。
第１図FIG. 1 is a partial plan view of an embodiment of the semiconductor device of the present invention;
FIG. 2 is a partial plan view of another embodiment, and FIG. 3 is a partial plan view of a conventional structure. 1.11.21--Semiconductor chip, 2a-2h, 12
a to 12h, 22a to 226... bonding pad, 3a to 3h, 13a to 13h, 23a to 2
3 e...-external lead, 4a to 4h, 14a
~14h. 24a to 2413... bonding portions, 5a to 5h. 15a to 15e, 25a to 25e...Bonding wire, θa to θe...Angle formed by bonding wire, d0 to d3...Gap distance between bonding pads, L
, ~L, ... bonding wire spacing dimension. Figure 1
Claims (1)
と、半導体チップ上に配設した複数個のボンディングパ
ッドとの間に夫々ボンディングワイヤを張設して両者を
電気的に接続した半導体装置において、前記各ボンディ
ングワイヤがチップ辺となす角度に基ずいて、このボン
ディングワイヤが接続されたボンディングパッドと、こ
れに隣接するボンディングパッドとの間隔寸法を、前記
角度の正弦の逆数に比例するように設定したことを特徴
とする半導体装置。 ２、ボンディングワイヤがチップとなす鋭角側の角度の
正弦の逆数に比例してボンディングパッドの間隔寸法を
設定してなる特許請求の範囲第１項記載の半導体装置。[Claims] 1. Bonding wires are stretched between the bonding portions provided on each of the plurality of external leads and the plurality of bonding pads arranged on the semiconductor chip to connect them electrically. In a semiconductor device connected to a semiconductor device, based on the angle that each bonding wire makes with the chip side, the distance between the bonding pad to which this bonding wire is connected and the adjacent bonding pad is determined by the sine of the angle. A semiconductor device characterized by being set to be proportional to a reciprocal number. 2. The semiconductor device according to claim 1, wherein the distance between the bonding pads is set in proportion to the reciprocal of the sine of the acute angle that the bonding wire makes with the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60139579A JPS621238A (en) | 1985-06-26 | 1985-06-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60139579A JPS621238A (en) | 1985-06-26 | 1985-06-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS621238A true JPS621238A (en) | 1987-01-07 |
Family
ID=15248545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60139579A Pending JPS621238A (en) | 1985-06-26 | 1985-06-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS621238A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5215940A (en) * | 1990-02-05 | 1993-06-01 | Orcutt John W | Wire looping method during wire bonding |
| JPH0653266A (en) * | 1992-08-03 | 1994-02-25 | Yamaha Corp | Semiconductor device |
-
1985
- 1985-06-26 JP JP60139579A patent/JPS621238A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5215940A (en) * | 1990-02-05 | 1993-06-01 | Orcutt John W | Wire looping method during wire bonding |
| JPH0653266A (en) * | 1992-08-03 | 1994-02-25 | Yamaha Corp | Semiconductor device |
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