JPS62112357A - Excessive input protective device - Google Patents
Excessive input protective deviceInfo
- Publication number
- JPS62112357A JPS62112357A JP25224285A JP25224285A JPS62112357A JP S62112357 A JPS62112357 A JP S62112357A JP 25224285 A JP25224285 A JP 25224285A JP 25224285 A JP25224285 A JP 25224285A JP S62112357 A JPS62112357 A JP S62112357A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- input voltage
- input
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001681 protective effect Effects 0.000 title description 3
- 230000003071 parasitic effect Effects 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 6
- 241000981595 Zoysia japonica Species 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 240000004760 Pimpinella anisum Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
Ａ、産業上の利用分野
本発明は、特に集積回路のための過入力保護装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION A. FIELD OF INDUSTRIAL APPLICATION The present invention relates in particular to over-input protection devices for integrated circuits.
Ｂ０発明の概要
バイポーラＩＣにおいて寄生ＭＯＳトランジスタが過入
力保護用素子として利用される。上記寄生ＭＯＳトラン
ジスタのドレインがアース電位に保たれる。上記寄生Ｍ
Ｏ５）−ランジスタのトレインはアイソレーション拡散
層であり、トレインとゲート、ソースと基板はそれぞれ
同電位にある。B0 Summary of the Invention In a bipolar IC, a parasitic MOS transistor is used as an over-input protection element. The drain of the parasitic MOS transistor is kept at ground potential. Parasitic M above
The train of the O5)-transistor is an isolation diffusion layer, and the train and gate, and the source and substrate are at the same potential.
Ｃ６従来の技術
従来集積回路例えば増幅回路の入力において、サージ等
過電圧入力による破壊を防ぐため、第３図に示すように
、入力端子に直列に保護抵抗を付加している。第１図中
、１は入力端子、２は保護抵抗を表わす。C6 Prior Art In order to prevent damage to the input of a conventional integrated circuit, such as an amplifier circuit, due to overvoltage input such as a surge, a protective resistor is added in series to the input terminal, as shown in FIG. In FIG. 1, 1 represents an input terminal and 2 represents a protection resistor.
Ｄ０発明が解決しようとする問題点
しかしながら、この方式では保護効果を高めるためには
抵抗値を大きくしなければならず、そうすると入力トラ
ンジスタのベース電流による電圧降下が大きくなる、等
の不都合を生じるため抵抗値を大きくできず、十分な保
護効果が得られないという欠点があった。D0 Problems to be Solved by the Invention However, in this method, the resistance value must be increased in order to increase the protection effect, which causes disadvantages such as an increase in voltage drop due to the base current of the input transistor. There was a drawback that the resistance value could not be increased and a sufficient protective effect could not be obtained.
本発明の目的は、保護抵抗の抵抗値を高くすることなく
、高い過入力保護効果を有する過入力保護装置を提供す
ることである。An object of the present invention is to provide an over-input protection device that has a high over-input protection effect without increasing the resistance value of the protection resistor.
Ｅ０問題点を解決するための手段
上記目的を達成するために、本発明による過入力保護装
置は、ソースとして動作する過入力電圧が印加される領
域、ゲートとして動作する電極およびドレインとして動
作する領域から成るＭＯＳトランジスタあるいは寄生Ｍ
ＯＳトランジスタと、上記ゲートとして動作する電極お
よびドレインとして動作する領域に接続された低電位手
段とを含むことを要旨とする。Means for Solving the E0 Problem In order to achieve the above object, the over-input protection device according to the present invention includes a region to which an over-input voltage is applied that operates as a source, an electrode that operates as a gate, and a region that operates as a drain. MOS transistor or parasitic M
The gist includes an OS transistor, and low potential means connected to the electrode that operates as the gate and the region that operates as the drain.
本発明の有利な実施の態様においては、上記低電位手段
はアースて′あり、」二足ドレインとして動作する領域
はバイポーラトランジスタのアイソレーション領域、上
記ソースとして動作する領域は上記バイポーラトランジ
スタのベース領域である。In an advantageous embodiment of the invention, the low potential means are grounded, and the region acting as a bipedal drain is the isolation region of the bipolar transistor and the region acting as the source is the base region of the bipolar transistor. It is.
Ｆ１作用
本発明はバイポーラＩＣにおける寄生ＭＯ５効果を利用
したものである。すなわち過入力電圧において寄生ＭＯ
Ｓトランジスタが導通状態となり。F1 Effect The present invention utilizes the parasitic MO5 effect in bipolar ICs. In other words, at excessive input voltage, the parasitic MO
The S transistor becomes conductive.
強制的に過入力電流を引き込み、ＩＣ内素子の破壊を防
ぐ。Forcibly draws in excessive input current to prevent destruction of elements within the IC.
Ｇ、実施例
以下に、図面を参照しながら、実施例を用いて本発明を
一層詳細に説明するが、それらは例示に過ぎず、本発明
の枠を越えることなしにいろいろな変形や改良があり得
ることは勿論である。G. EXAMPLES The present invention will be explained in more detail below using examples with reference to the drawings, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course it is possible.
第１図は、本発明による過入力保護装置の断面図で、図
中３はＩＣ基板、４は埋込み層、５はエピタキシャル成
長層、６．６’はアイソレーション層、７はベース拡散
層、８はエミッタ拡散層。FIG. 1 is a sectional view of an over-input protection device according to the present invention, in which 3 is an IC substrate, 4 is a buried layer, 5 is an epitaxial growth layer, 6.6' is an isolation layer, 7 is a base diffusion layer, and 8 is the emitter diffusion layer.
９．１０．１」 はＡ１電極、１２は絶縁膜である。こ
こで、ベース拡散層７をソース、左側アイソレーション
層６をドレイン、端子Ａに接続されたｆｌ！極１極左０
−トとするＭＯＳトランジスタが形成されている。9.10.1'' is the A1 electrode, and 12 is an insulating film. Here, the base diffusion layer 7 is the source, the left isolation layer 6 is the drain, and fl! is connected to the terminal A. pole 1 pole left 0
- A MOS transistor is formed.
いま、第２図に示すように、端子Ａをアニスに落し、端
子Ｂに入力電圧を加えるとする。入力電圧が高くなると
、Ｎ型エピタキシャル層５の電位も高くなるが、ゲート
電位はＯｖであるので。Now, as shown in FIG. 2, assume that terminal A is dropped into an anis and an input voltage is applied to terminal B. As the input voltage increases, the potential of the N-type epitaxial layer 5 also increases, but the gate potential is Ov.
Ｎ型エピタキシャル層５とゲート間の電位差は、Ｎ型エ
ピタキシャル成長層表面が反転し易くなる方向で増加す
る。入力電圧がある一定電圧を越えるとゲート電極と対
向しているＮ型エピタキシャル成長層の表面は反転し、
ソーχ苓ルイン間に電流通路ができる。すなわち、過入
力があった場合、このＭＯＳトランジスタを通してアー
スへ電流が流れ落ちてしまう。したがって、ＩＣ内の素
子は保護される。通常のＩＣでは、２０〜４０ ＶでＮ
型エピタキシャル成長層の表面は反転する。The potential difference between the N-type epitaxial layer 5 and the gate increases in the direction in which the surface of the N-type epitaxial growth layer is more likely to be inverted. When the input voltage exceeds a certain voltage, the surface of the N-type epitaxial growth layer facing the gate electrode is reversed.
A current path is created between the two. That is, if there is an excessive input, current will flow down to ground through this MOS transistor. Therefore, the elements within the IC are protected. In a normal IC, N at 20 to 40 V
The surface of the type epitaxially grown layer is inverted.
Ｈ０発明の詳細
な説明した通り、本発明によれば、低抵抗を使いながら
、効果的な過入力保護ができる。As described in detail about the H0 invention, according to the present invention, effective over-input protection can be achieved while using a low resistance.
第１図は本発明による過入力保護装置の断面図、第２図
は本発明による過入力保護装置の回路図、第３図は従来
の過入力保護回路の回路図である６３・・・・・・・・
・ＩＣ基板、４・・・・・・・・・埋込み層、５・・・
・・・・・エピタキシャル成長層、６，６′・・・・・
・・・・アイソレーション層、７・・・・・・・・・ベ
ース拡散層、８・・・・・・・・エミッタ拡散層′、９
・・・・・・・・・Ａｌ電極（入力）、１０・・・・・
・・・・Ａｌ電極（ゲート）、１１・・・・・・・・Ａ
１電極（接地）、１２・・・・・・・・・絶縁膜。
特許出願人 クラリオン株式会社
手続補正書
１ 事件の表示
昭和６０年特許康 第２５２２４２号
３、 補正をする者
事件との関係 特軒出−人
住所
名 称 （１４８） クラリオン株式会社４代理人〒
１０５
住 所 東京都港区芝３丁目２番１４号芝三丁目ビル
第１図及び第２図に別紙の通り補正する。Fig. 1 is a sectional view of an over-input protection device according to the present invention, Fig. 2 is a circuit diagram of an over-input protection device according to the invention, and Fig. 3 is a circuit diagram of a conventional over-input protection circuit.・・・・・・
・IC board, 4...Buried layer, 5...
...Epitaxial growth layer, 6,6'...
...Isolation layer, 7...Base diffusion layer, 8...Emitter diffusion layer', 9
......Al electrode (input), 10...
...Al electrode (gate), 11...A
1 electrode (ground), 12... Insulating film. Patent Applicant Clarion Co., Ltd. Procedural Amendment 1 Case Indication Patent Law No. 252242 No. 3 of 1985 Relationship to the case of the person making the amendment Name and address of the applicant (148) Clarion Co., Ltd. 4 Agents〒
105 Address: Shiba 3-chome Building, 3-2-14 Shiba, Minato-ku, Tokyo Amended Figures 1 and 2 as shown in the attached sheet.
Claims (4)
域、ゲートとして動作する電極およびドレインとして動
作する領域から成るＭＯＳトランジスタあるいは寄生Ｍ
ＯＳトランジスタ、および （ｂ）上記ゲートとして動作する電極およびドレインと
して動作する領域に接続された低電位手段 を含むことを特徴とする過入力保護装置。(1) (a) A MOS transistor or parasitic transistor consisting of a region to which excessive input voltage is applied that operates as a source, an electrode that operates as a gate, and a region that operates as a drain.
An over-input protection device comprising: an OS transistor; and (b) low potential means connected to the electrode acting as the gate and the region acting as the drain.
、特許請求の範囲第１項記載の過入力保護装置。(2) The over-input protection device according to claim 1, wherein the low potential means is ground.
ランジスタのアイソレーション領域であることを特徴と
する、特許請求の範囲第１項記載の過入力保護装置。(3) The over-input protection device according to claim 1, wherein the region that operates as the drain is an isolation region of a bipolar transistor.
トランジスタのベース領域であることを特徴とする、特
許請求の範囲第３項記載の過入力保護装置。(4) The over-input protection device according to claim 3, wherein the region that operates as the source is a base region of the bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25224285A JPS62112357A (en) | 1985-11-11 | 1985-11-11 | Excessive input protective device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25224285A JPS62112357A (en) | 1985-11-11 | 1985-11-11 | Excessive input protective device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62112357A true JPS62112357A (en) | 1987-05-23 |
| JPH0551183B2 JPH0551183B2 (en) | 1993-07-30 |
Family
ID=17234488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25224285A Granted JPS62112357A (en) | 1985-11-11 | 1985-11-11 | Excessive input protective device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62112357A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE37593E1 (en) | 1988-06-17 | 2002-03-19 | Hitachi, Ltd. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
| USRE40132E1 (en) | 1988-06-17 | 2008-03-04 | Elpida Memory, Inc. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
-
1985
- 1985-11-11 JP JP25224285A patent/JPS62112357A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE37593E1 (en) | 1988-06-17 | 2002-03-19 | Hitachi, Ltd. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
| USRE40132E1 (en) | 1988-06-17 | 2008-03-04 | Elpida Memory, Inc. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0551183B2 (en) | 1993-07-30 |
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