JPS6210741A - Memory device - Google Patents

Abstract

PURPOSE:To correspond to the increase of a memory by inputting signals from two means, changing over the signals from two means by the external command, sending to an address buffer circuit and controlling an address signal impressed to a memory part. CONSTITUTION:At the time of using usually the memory, the address scope set at an optional address setting circuit 6 is transmitted through a control circuit 7 to an address buffer circuit 2 and an address checking circuit 4, and the memory access is executed in the set memory address scope. When the address signal is transmitted over the address scope from a CPU 1, the error is detected by an address checking circuit 4, and the access, which does not execute the error report to the CPU 1, is made invalid. At the time of maintenance, by the external command from the CPU 1, the control circuit 7 sends the address scope of an actual address setting circuit 5 to the address buffer circuit 2 and the address checking circuit 4, and executes the test up to the maximum address of the mounted memory. Thus, the increase can be easily executed only by changing the accessible scope to the increase in the memory board which is to be given larger capacity.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a storage device.

[Conventional technology]

The conventional storage device has an address control method as shown in FIG. That is, address signals AO, AI, . . . , Axx transmitted from the CPU 1 are applied to the memory section 3 via the address buffer circuit 2.

At this time, the address buffer circuit 2 receives a signal created by the real address setting circuit 5 based on the information MO, Ml, . An address signal A that selects memory blocks BO, Bl, . . ., Bx of the memory section 3 by a signal indicating the maximum range of accessible addresses.
xO, Axl...A memory block HO installed in the memory section 3 by controlling A x x.

B1...Bx is selected.

In addition, the address check circuit 4 uses address signals AxO, Axl...Axx for selecting memory blocks BO, Bl...Bx from CPIJI and a signal from the real address setting circuit 5 to If an access is made beyond the memory address actually installed, an error report is sent to the CPU.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional storage device, the address control method is within the range of the mounted memory due to the way the information MO, Ml...Mx representing the mounting state is set from the memory section 3. The access range during normal use can be set arbitrarily, but on the other hand, if part of the installed memory has been set, the part beyond the set access range cannot be accessed during maintenance. Since it is not tested beforehand, there is a drawback that operation cannot be guaranteed if the access range is changed and the access range is changed and used immediately.

In addition, in the case of conventional storage devices, memory expansion was supported by preparing a memory board with a memory capacity corresponding to each expansion unit, but the memory board used in this storage device was It is desirable from the viewpoint of maintenance that both the expansion section and the basic section use the same memory board.
As the density of ICs increases, the capacity per memory board also increases, and the conventional selection of memory blocks has the disadvantage that it cannot accommodate the expansion of memory.

[Means for solving problems]

The storage device of the present invention includes a means for arbitrarily setting an accessible address range, a means for setting an accessible address range up to the maximum address of the real memory storage, and input signals from the above two means. The control circuit also includes a control circuit that switches signals from the two means by an external voltage switch, sends them to the address buffer circuit, and controls the address signals to be stamped in the memory section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram containing one embodiment of the present invention.

In FIG. 1, the CPUI sends address signals AQ, AI, . . . , Axx to the storage device M. The address signals AxO, Ax1...Axx are particularly used for memory blocks Bo, Bl...- of the memory section 3.
・This is a signal for selecting Bx. When the address buffer circuit 2 receives the address signals AO, Al...Axx, it selects the memory blocks BO, Bl...Bx of the memory section 3 in combination with the signal from the control circuit 7. Create and send signals to select memory blocks BO, Bl...-Bx, and send address signals AxO, Axl... to memory boards in valley memory blocks BO, Bl...-Bx. ---Distributes Axx. Memory section 3 is block BQ.

B1... This is a memory section composed of Bx.

The real address setting circuit 5 is a circuit that receives memory mounting information MO, Ml...Mx from the memory section 3 and sets the maximum address range in which the memory is actually mounted.The arbitrary address setting circuit 6 Input information DO, I) 1...
. . . This is a circuit that arbitrarily sets how far the memory address of this storage device M is valid for use using Dx. The input information DO, DI...Dx may be transmitted by software instructions from the CPU 1, or may be set manually by giving a mechanical switch signal, but this arbitrary address setting circuit Although the address range set in step 6 may be equal to the address range set in the real address setting circuit 5, it cannot be set beyond the address range. The control circuit 7 inputs signals from the arbitrary address setting circuit 6 and the real address setting circuit 5, and switches these signals according to the maintenance command signal from the CPUI to set the address range to the address buffer circuit 2 and address check circuit 4. This is a circuit that sends out control signals. Here, the address check circuit 4 is a circuit that checks whether the address transmitted from the CPUI is within an accessible range, and reports an error to the CPU 1 in the event of an error.

With the above configuration, when using normal memory, the CP
Since no maintenance command is received from the UI, the address range set by the arbitrary address setting circuit 6 is sent to the address buffer circuit 2 and address check circuit 4 via the control circuit 7, and the memory within the set memory address range is Access is made. When an address signal is transmitted from the CPU 1 beyond the address range, the address check circuit 4 detects an error, reports the error to the CPU 1, and invalidates the access. Also, during maintenance, the CPU
1, the control circuit 7 operates to send the address range of the real address setting circuit 5 to the address buffer circuit 2 and the address check circuit 4, and perform a test up to the maximum address of the mounted memory.

〔Effect of the invention〕

The storage device of the present invention has a function that allows the accessible range to be arbitrarily changed within the installed memory capacity, thereby eliminating the need to replace the memory board with one with a different installed capacity when memory is expanded. Moreover, when increasing the number of memory boards, it is possible to easily increase the number of memory boards by simply changing the accessible range.

[Brief explanation of drawings]

FIG. 1 is a block diagram including an embodiment of the present invention, and FIG. 2 is a block diagram including an example of the conventional art. 1...CPU%M, M'...Storage device, 2...Address buffer circuit, 3...
・Memory section, 4...Address check circuit, 5
...Real address setting circuit, 6...Arbitrary address setting circuit, 7...Control circuit, AO~A
xx...Address 1 word, BO~Bx...
...Memory block, DO-Dx...Arbitrary address range setting information, M O-M x...Real address@circle setting information. / ・ Agent: Susumu Uchihara, patent attorney -〇Q-'b

Claims (1)

[Claims] arbitrary address setting means for arbitrarily setting an accessible range of memory addresses; real address setting means for setting an accessible address range up to the maximum address of the installed real memory capacity; the arbitrary address setting means and the real address. 1. A storage device comprising: a control circuit which inputs a signal from a setting means and applies an address signal to a memory section by switching the address signal depending on an external command between normal memory use and maintenance.