KR890011276A - Master Controller of RSS Interface in Distributed Control Electronic Switching System - Google Patents

Abstract

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Description

Master Controller of RSS Interface in Distributed Control Electronic Switching System

Since this is an open matter, no full text was included.

1 is a main control block diagram of an RSS interface in an electronic switch according to the present invention.

2 is a concrete system diagram of FIG.

Claims (1)

In the main control device of the RSS interface of the electronic switching system of the distributed control method, the MPU 10 which processes the system as a 16-bit microprocessor and a clock generator which oscillates at a predetermined frequency and supplies the clock of the MPU 10 and the system ( 20) and an address and data (16 bits) are selected by the control signal of the MPU 10, generating data for I / O (8 bits) and simultaneously determining the data direction and selecting the first and second I / O. After selecting the corresponding memory by the system bus controller 30 generating the control signal, the control signal of the MPU 10 and the output of the system bus controller 30, the data in the memory is processed into even, odd bytes, or word multiples. And a reset signal to the MPU 10 by a power-on reset, a system reset or a manual reset, and a memory and an I / O control unit 40 for generating a third and fourth I / O selection control signals. The reset unit 50 for applying the An interrupt controller 60 enabled by the first I / O selection control signal of the system bus controller 30 and controlling the priority of an external interrupt signal and applying the priority to the MPU 10 according to the priority; When interfacing with an external memory or an I / O device, the VME bus control unit 70 generates bus requests, bus request acceleration and bus request acknowledge approval signals required for VME bus control, and in-system memory or I The weight generation unit 80 that weights the MPU 10 for one clock period during / O access and external memory or I / O access, and the NMI source is enabled or disabled by controlling the clear (CLR) signal. It is selected by the NMI control unit 90 and the second I / O control signal of the system bus control unit 30 output to the MPU (10) and according to the output of the clock generator 20 and the MPU (10) MMC between system users Selected by the MMC interface unit 100 and the third I / O control signal of the memory and I / O control unit 40 and operated by the output of the clock generation unit 20 to occur in a data link transmission company. The H / W monitoring unit 110 and the memory and I / O control unit 40 are configured to monitor faults and states and to output the interrupt control unit 60 when an error occurs and to generate a clear (CLR) signal that is an NMI control signal. A data link interface controller 120 which is selected by a fourth I / O control signal to interface system data with external data through a NITA link according to the output of the clock generator 20, and system data and a data link. And an alarm source access unit (130) for generating a state signal of an alarm source by interfacing external data and applying it to the H / W monitoring unit (110). ※ Note: The disclosure is based on the initial application.