KR940008489A

KR940008489A - Multi-bus control method using interrupt method

Info

Publication number: KR940008489A
Application number: KR1019920017349A
Authority: KR
Inventors: 김경진
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1992-09-23
Filing date: 1992-09-23
Publication date: 1994-04-29
Also published as: KR970005832B1

Abstract

본 발명은 인터럽트 방식을 이용한 다중 버스 조절 방법에 관한 것으로, 제1프로세서(100)의 메인프로세싱(1)에 의해 인터럽트 신호를 발생(2)하여 메인프로세싱(3)을 통해 상기 제1프로세서(100)는 버스 사용권을 회복(4)하고 다시 상기 메인프로세싱(1)으로 복귀하는데 제1단계, 상기 제1단계 수행 중에 상기 제2프로세서(200)에서 발생된 인터럽트 신호(2)를 제2프로세서(200)가 메인프로세싱(5)에 의해 판단(6)하여 인터럽트 신호를 인식하면 버스 사용 요구를 표시하는 신호를 출력하여(7) 버스 사용 인가 신호(/BB₂)가 입력 되는가 판단(8)하는 입력되면 버스를 사요(9)하고 버스 사용 완료 신호(/BR₂)를 출력하고 메인프로세싱(5)으로 복귀하거나 제2인터럽트 신호를 발생(11)하여 상기 제1프로세서(200)의 버스 사용권을 회복(4)시켜 주는 제3단계에 의해 수행되는 것을 특징으로 하는 인터럽트 방식을 이용한 다중 버스 조절 방법에 관한 것이다.The present invention relates to a multi-bus adjustment method using an interrupt method, and generates an interrupt signal by main processing (1) of the first processor 100 (2) and through the main processing (3) the first processor (100). ) Recovers a bus right (4) and returns to the main processing (1). The interrupt signal 2 generated by the second processor 200 during the first step and the first step is transmitted to the second processor ( When the 200 recognizes the interrupt signal by the main processing 5 (6), it outputs a signal indicating the bus usage request (7) and determines whether the bus usage authorization signal (/ BB ₂ ) is input (8). When inputted, use the bus (9), output the bus use completion signal (/ BR ₂ ) and return to the main processing (5) or generate a second interrupt signal (11) to renew the bus right of the first processor (200). Carried out by a third step of recovery (4) It relates to a multi-bus control method using an interrupt method characterized in that.

Description

Multi-bus control method using interrupt method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 다중프로세서 시스템을 도시한 도면.1 illustrates a multiprocessor system in accordance with the present invention.

제2도는 본 발명에 따른 인터럽트 방식을 이용한 다중 버스 조절 흐름도.2 is a flowchart illustrating a multiple bus adjustment using an interrupt scheme according to the present invention.

제3도는 여러 소자에 대한 본 발명에 따른 인터럽트 방식을 이용한 다중 버스 조절 흐름도.3 is a flow chart of multiple bus regulation using an interrupt scheme in accordance with the present invention for various devices.

제4도는 상기 제2도의 타이밍도.4 is a timing diagram of FIG.

Claims

In the multi-bus control method using an interrupt method, an interrupt signal is generated (2) by the main processing (1) of the first processor (100) and the first processor (100) uses a bus right through the main processing (3). To recover (4) and return to the main processing 1 again, the second processor 200 mains interrupt signal 2 generated by the first processor 100 during the first step and the first step. A second step of judging (6) by the processing (5) and outputting a signal indicating the bus usage request when receiving the interrupt signal (7) determining whether the bus usage authorization signal (/ BB ₂ ) is input (8) When the bus use authorization signal (/ BB ₂ ) is input after performing the second step, the bus is used (9), the bus use completion signal (/ BR ₂ ) is output, the main processing (5) is returned, and the second interrupt is performed. Generates a signal (11) to issue the bus right of the first processor (100). A multiple bus adjustment method using an interrupt method, characterized in that performed by a third step of recovering (4).

2. The method of claim 1, wherein if the number of devices on the bus is n (n = 1, 2, 3, ...), the operation is repeatedly performed for each device.

※ Note: The disclosure is based on the initial application.