KR950029953A - Universal Response Signal Generator for S-BUS Systems - Google Patents

Universal Response Signal Generator for S-BUS Systems Download PDF

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Publication number
KR950029953A
KR950029953A KR1019940009494A KR19940009494A KR950029953A KR 950029953 A KR950029953 A KR 950029953A KR 1019940009494 A KR1019940009494 A KR 1019940009494A KR 19940009494 A KR19940009494 A KR 19940009494A KR 950029953 A KR950029953 A KR 950029953A
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South Korea
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response signal
signal generator
signal
size data
data
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KR1019940009494A
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Korean (ko)
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KR960009671B1 (en
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이승섭
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배순훈
대우전자 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0034—Sun microsystems bus [SBus]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

본 범용응답신호발생장치는 주장치와 종속장치간의 데이터전송을 위하여 SBus를 사용하는 컴퓨터시스템에서 주장치와 종속장치간의 전송가능한 사이즈가 제한되지 않도록 하기 위해, 주장치로 부터 인가되는 데이터사이즈에 대하여 적응적으로 응답할 수 있도록 하기 위한 것이다. 이를 위하여 범용응답신호발생장치는 SBus를 통해 주장치로 부터 인가되는 전송데이터의 사이즈데이터와 제1소정수의 어드레스신호의 논리조합에 의해 응답신호를 발생하기 위한 응답신호발생부; 사이즈데이터를 디코드하기 위한 제1디코더; 제1디코더의 사이즈데이터 디코드신호, SBus를 통해 주장치로 부터 인가된 어드레스 스트로브신호 및 시스템클럭신호에 의하여 주장치와 종속장치간의 전송속도가 매칭되도록 제어하기 위한 전송속도제어부; 전송속도제어부의 출력신호와 사이즈데이터 디코드신호의 논리조합 결과에 의해 인에이블 제어되어 응답신호 발생부에서 출력되는 응답신호를 주장치로 전송되도록 SBus로 전송하는 버퍼를 포함하도록 구성된다.This universal response signal generating device is adaptively adapted to the data size applied from the main device so that the transferable size between the main device and the slave device is not limited in a computer system using the SBus for data transmission between the main device and the slave device. It is intended to be able to respond. To this end, the general-purpose response signal generator includes a response signal generator for generating a response signal by a logical combination of the size data of the transmission data applied from the main apparatus through the SBus and the first predetermined integer address signal; A first decoder for decoding the size data; A transmission speed control unit for controlling a transmission speed between the main device and the slave device according to the size data decode signal of the first decoder, the address strobe signal applied from the main device through the SBus, and the system clock signal; And a buffer which is enabled by the result of the logical combination of the output signal of the transmission rate control unit and the size data decode signal, and transmits the response signal output from the response signal generator to the SBus to be transmitted to the main device.

Description

에스버스 시스템용 범용 응답신호발생장치Universal Response Signal Generator for S-BUS Systems

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

도면은 본 발명에 따른 범용 응답신호발생장치의 상세한 회로도.Figure is a detailed circuit diagram of the general-purpose response signal generator according to the present invention.

Claims (7)

SBus를 통해 주장치와 종속장치간의 데이터를 전송하기 위한 컴퓨터시스템에 있어서; 상기 SBus를 통해 상기 주장치로 부터 인가되는 전송데이터의 사이즈데이터와 제1소정수의 어드레스신호의 논리조합에 의해 응답신호를 발생하기 위한 응답신호발생부; 상기 사이즈데이터를 디코드하기 위한 제1디코더; 상기 제1디코더의 사이즈데이터 디코드신호, 상기SBus를 통해 상기 주장치로 부터 인가된 어드레스 스트로브신호 및 시스템클럭 신호에 의하여 상기 주장치와 상기 종속장치간의 전송속도가 매칭되도록 제어하기 위한 전송속도제어부; 상기 전송속도제어부의 출력신호와 상기 사이즈데이터 디코드신호의 논리조합결과에 의해 인에이블 제어되어 상기 응답신호 발생부에서 출력되는 응답신호를 상기 주장치로 전송되도록 상기 SBus로 전송하는 버퍼를 포함함을 특징으로 하는 범용 응답신호 발생장치.A computer system for transferring data between a master device and a slave device via an SBus; A response signal generator for generating a response signal by a logical combination of the size data of the transmission data applied from the main apparatus via the SBus and the first predetermined integer address signal; A first decoder for decoding the size data; A transmission speed control unit for controlling a transmission speed between the main device and the slave device according to a size data decode signal of the first decoder, an address strobe signal and a system clock signal applied from the main device through the SBus; And a buffer which is enabled by the result of the logical combination of the output signal of the transmission rate control unit and the size data decode signal and transmits the response signal output from the response signal generator to the SBus to be transmitted to the main device. General-purpose response signal generator. 제1항에 있어서, 상기 범용 응답신호발생장치는 상기 사이즈데이터 디코더에서 출력되는 디코드값들의 논리조합에 의하여 현재 인가된 사이즈데이터의 논리신호를 검출하기 위한 사이즈데이터 검출부를 더 포함함을 특징으로 하는 범용 응답신호 발생장치.The apparatus of claim 1, wherein the universal response signal generator further comprises a size data detector for detecting a logic signal of size data currently applied by a logical combination of decode values output from the size data decoder. General purpose response signal generator. 제2항에 있어서, 상기 전송속도제어부는 상기 시스템클럭에 의하여 소정시간 카운트하는 카운터와, 상기 사이즈데이터검출부에서 출력되는 사이즈 데이터의 논리신호와 상기 어드레스스트로브신호의 논리조합에 의하여 상기 카운터의 인에이블 상태를 제어하기 위한 인에이블제어회로를 포함함을 특징으로 하는 범용 응답신호 발생장치.3. The method of claim 2, wherein the transmission rate control unit enables the counter by a counter that counts a predetermined time by the system clock, a logical combination of the size data output from the size data detection unit, and the address strobe signal. A general-purpose response signal generator, characterized in that it comprises an enable control circuit for controlling the state. 제1항에 있어서, 상기 응답신호발생부는 상기 사이즈데이터에 대하여 하기와 같은 방식의 논리조합에 의하여 상기 응답신호를 발생함을 특징으로 하는 범용 응답신호 발생장치.The general-purpose response signal generator of claim 1, wherein the response signal generator generates the response signal with respect to the size data by a logical combination as follows. 제1항에 있어서, 상기 범용 응답신호발생장치는 상기 응답신호발생부로 부터 출력된 응답신호를 디코드하기 위한 제2디코더와 상기 제2디코더에서 디코드된 결과신호중 데이터전송시 데이터 얼라인먼트에 의하여 발생되는 에러상태와 아이들/대기상태중 어느 하나의 발생여부를 검출하여 상기 버퍼가 디스에이블되도록 상기 전송속도제어부로 출력하기 위한 검출부를 더 포함함을 특징으로 하는 범용 응답신호발생장치.The apparatus of claim 1, wherein the universal response signal generator is an error generated by data alignment during data transmission between a second decoder for decoding a response signal output from the response signal generator and a result signal decoded by the second decoder. And a detection unit for detecting whether one of a state and an idle / standby state is generated and outputting the buffer to the transmission rate control unit so that the buffer is disabled. 제5항에 있어서, 상기 전송속도제어부는 상기 시스템클럭에 의하여 소정시간 카운트하는 카운터와, 상기 사이즈데이터디코더에서 출력되는 디코드결과값, 상기 어드레스스트로브신호 및 상기 검출부로 부터의 검출신호의 논리조합에 의하여 상기 카운터의 인에이블상태를 제어하기 위한 인에이블제어회로를 포함함을 특징으로 하는 범용응답신호 발생장치.6. The data rate control apparatus as claimed in claim 5, wherein the transmission speed control unit is configured to perform a logical counting of a counter counting a predetermined time by the system clock, a decoding result value output from the size data decoder, the address strobe signal and a detection signal from the detection unit. And an enable control circuit for controlling the enable state of the counter. 제6항에 있어서, 상기 인에이블 제어회로는 상기 디코드결과값과 상기 어드레스 스트로브신호를 논리합한뒤, 논리합한 결과와 상기 검출신호를 논리합한 결과신호에 의하여 상기 인에이블상태를 제어하도록 구성됨을 특징으로 하는 범용 응답신호발생장치.7. The enable control circuit of claim 6, wherein the enable control circuit is configured to control the enable state according to the result of the logical sum of the decode result value and the address strobe signal, and the result of the logical sum of the result signal and the detection signal. General purpose response signal generator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940009494A 1994-04-30 1994-04-30 General acknowledgement signal generator for sbus system KR960009671B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451170B1 (en) * 2000-09-20 2004-10-02 엘지전자 주식회사 Release-guard signal generation circuit for read/write for processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451170B1 (en) * 2000-09-20 2004-10-02 엘지전자 주식회사 Release-guard signal generation circuit for read/write for processor

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