KR910003971A - Telex line control circuit and control method - Google Patents

Telex line control circuit and control method Download PDF

Info

Publication number
KR910003971A
KR910003971A KR1019890010355A KR890010355A KR910003971A KR 910003971 A KR910003971 A KR 910003971A KR 1019890010355 A KR1019890010355 A KR 1019890010355A KR 890010355 A KR890010355 A KR 890010355A KR 910003971 A KR910003971 A KR 910003971A
Authority
KR
South Korea
Prior art keywords
telex
output device
parallel input
processing unit
central processing
Prior art date
Application number
KR1019890010355A
Other languages
Korean (ko)
Other versions
KR940005212B1 (en
Inventor
이경준
전용태
이문우
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019890010355A priority Critical patent/KR940005212B1/en
Publication of KR910003971A publication Critical patent/KR910003971A/en
Application granted granted Critical
Publication of KR940005212B1 publication Critical patent/KR940005212B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L15/00—Apparatus or local circuits for transmitting or receiving dot-and-dash codes, e.g. Morse code

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

내용 없음.No content.

Description

텔렉스 회선제어 회로 및 제어방법Telex line control circuit and control method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 회선 제어회로 구성도,3 is a block diagram of a circuit control circuit according to the present invention;

제4도는 본 발명에 따른 회선 제어 방법도,4 is a circuit control method according to the present invention,

제5도는 송신용 타이머 인터럽트 흐름도,5 is a timer interrupt flowchart for transmission;

제6도는 수신용 타이머 인터럽트 흐름도.6 is a flowchart for receiving a timer interrupt.

Claims (5)

텔렉스 회선제어신호를 입출력 하는 병렬 입출력장치(3d), 텔렉스 회선제어 회로에서 인터럽트 서비스 루틴을 수행하고 병렬 입출력 장치를 엑세스하여 텔렉스 신호 방식에 따른 제어 신호를 송 수신하는 동작과 인터럽트 루틴에서 데이타 송 수신 동작을 행할 수 있도록 제어하는 중앙 처리장치(3a), 송수신할 데이타와 인터럽트 카운터값과 데이터 송신 비트의 스텝 카운터 값 및 인터럽트 루틴에서의 데이타 송수신 제어 명령의 내용을 저장하는 메모리(3b), 및 일정한 주기로 중앙 처리장치에서 인터럽트를 요구하는 송신용 및 수신용타이머(3c)를 구비하고 있는 것을 특징으로 하는 텔렉스 회선 제어 회로.A parallel input / output device (3d) for inputting and receiving a telex line control signal and an interrupt service routine are executed in the telex line control circuit and the parallel input / output device is accessed to transmit and receive a control signal according to the telex signal method. A central processing unit 3a for controlling the operation, a memory 3b for storing the data to be transmitted and received, the step counter value of the data transmission bit and the step counter value of the data transmission bit, and the contents of the data transmission and reception control instruction in the interrupt routine, and And a transmission and reception timer (3c) for requesting interruption at a central processing unit at periodic intervals. 제1항에 있어서, 회선 접속 신호 발생 및 출력과 데이타 입출력을 상기 병렬 입출력장치(3d)의 비트에 할당한 것을 특징으로 하는 텔렉스 회선 제어회로.The telex line control circuit according to claim 1, wherein the line connection signal generation and output and data input / output are allocated to the bits of the parallel input / output device (3d). 제1항에 있어서, 상기 타이머의 인터럽트 횟수를 카운터하여 신호 지연시간을 결정하고 상기 중앙 처리 장치(3a)가 병렬 입출력 장치(3d)의 해당 비트를 리드/라이트 하여 텔렉스 신호 방식에 따른 신호 발생 및 검출을 수행하도록 한 것을 특징으로 하는 텔렉스 회선 제어 회로.The method according to claim 1, wherein the signal delay time is determined by counting the number of interrupts of the timer, and the CPU 3a reads / writes a corresponding bit of the parallel input / output device 3d to generate a signal according to a telex signal method. A telex line control circuit, characterized in that detection is performed. 병렬 입출력 장치(3d), 상기 병렬입출력장치(3d)에 연결된 중앙처리장치 (3a), 상기 중앙처리장치(3a)에 연결된 메모리(3b), 및 상기 중앙 처리 장치에서 인터럽트를 요구하는 송신용 및 수신용 타이머(3c)로 구성된 텔렉스 회선 제어 회로에 있어서, 텔렉스 데이타 송신시 인터럽트 서비스 루틴에서 송신해야할 정보를 각각 스텝으로 나누는 제1단계, 인터럽트 발생횟수를 카운터하는 제2단계, 각 스텝별로 수행하여야 할 동작을 결정하는 제3단계, 및 각 동작별로 수행하는 절차에 따라 송신하는 제4단계로 이루어진 것을 특징으로 하는 텔렉스 회선 제어 방법.A parallel input / output device 3d, a central processing unit 3a connected to the parallel input / output device 3d, a memory 3b connected to the central processing unit 3a, and a transmission requesting an interrupt from the central processing unit; and In a telex circuit control circuit composed of a reception timer 3c, a first step of dividing information to be transmitted by an interrupt service routine in a telex data transmission into steps, a second step of countering the number of interrupt occurrences, and a step to each step And a fourth step of transmitting according to a third step of determining an operation to be performed, and a fourth step of transmitting according to a procedure performed for each operation. 병렬 입출력장치(3d), 상기 병렬 입출력장치(3d)에 연결된 중앙 처리 장치(3a), 상기 중앙 처리장치(3a)에 연결된 메모리(3b), 및 상기 중앙 처리장치에서 인터럽트를 요구하는 송신용 및 수신용 타이머(3c)로 구성된 텔렉스 회선제어회로에 있어서, 텔렉스 데이타 수신시 인터럽트 루틴에서 수신에 따른 동작을 각각의 스텝으로 나누는 제1단계, 인터럽트 발생 때마다 스타트 비트를 검출하는 제2단계, 상기 스타트 비트가 검출되면 인터럽트 발생횟수에 따라 스텝별로 상기 병렬 입출력 장치(3d)의 해당 비트값을 리드하여 데이타를 수신하는 제3단계 및 5비트 정보를 수신하면 스탑비드 5 검출하여 데이타를 수신하는 제4단계로 이루어진 것을 특징으로 하는 텔렉스 회선 제어 방법.A parallel input / output device 3d, a central processing unit 3a connected to the parallel input / output device 3d, a memory 3b connected to the central processing unit 3a, and a transmission requesting an interrupt from the central processing unit; and A telex line control circuit comprising a reception timer 3c, comprising: a first step of dividing an operation according to a reception by an interrupt routine in reception of a telex data in each step; a second step of detecting a start bit each time an interrupt occurs; A third step of receiving data by reading the corresponding bit value of the parallel input / output device 3d step by step when the start bit is detected; and by detecting the stop bead 5 by receiving 5-bit information. Telex line control method characterized in that consisting of four steps. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890010355A 1989-07-21 1989-07-21 Telex line control apparatus and controlling method thereof KR940005212B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890010355A KR940005212B1 (en) 1989-07-21 1989-07-21 Telex line control apparatus and controlling method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890010355A KR940005212B1 (en) 1989-07-21 1989-07-21 Telex line control apparatus and controlling method thereof

Publications (2)

Publication Number Publication Date
KR910003971A true KR910003971A (en) 1991-02-28
KR940005212B1 KR940005212B1 (en) 1994-06-13

Family

ID=19288286

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890010355A KR940005212B1 (en) 1989-07-21 1989-07-21 Telex line control apparatus and controlling method thereof

Country Status (1)

Country Link
KR (1) KR940005212B1 (en)

Also Published As

Publication number Publication date
KR940005212B1 (en) 1994-06-13

Similar Documents

Publication Publication Date Title
KR830008232A (en) Communication Multiplexer with Variable Priority Scheme Using ROM
KR880000858A (en) Multiprocessor Level Change Synchronizer
KR880009307A (en) Direct memory access controlled system
KR900702688A (en) Disconnection position detection device of serial controller
KR880700577A (en) Data channel device
KR910003971A (en) Telex line control circuit and control method
KR910003505A (en) Communication method between central processing units
KR950005074A (en) Data communication system and apparatus for the system
KR850006090A (en) Data transmission system
JPS6133224B2 (en)
JPS5617442A (en) Parity error processing system
KR970004520A (en) Packet data transmission device and transmission method
KR940004415A (en) I / O interface controller
KR890015560A (en) Facsimile Data Transfer Processing Method
KR950029953A (en) Universal Response Signal Generator for S-BUS Systems
KR960016236A (en) Data transmission circuit
JPS577647A (en) Fault processing system
KR960042391A (en) DM controller in high speed medium computer system
KR880005528A (en) How to determine terminal speed and format of modem using "AT"
KR880014787A (en) Data processing method of simulation transmitter
KR880008169A (en) Microcomputer System for Communication
KR970016994A (en) Apparatus and method for data communication between processors via shared memory
KR930011499A (en) Cell Multiplexing Device in ATM System
KR920011135A (en) Asynchronous Terminal System Preventing Data Loss
KR950004006A (en) Direct memory access (DMA) transmission error correction method and apparatus

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19980313

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee