JPS6133224B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data processing that performs interrupt control in an electronic computer having a multiprocessor configuration.

Conventionally, in a data processing device having a plurality of processors, as a method for transmitting an interrupt request such as an input/output interrupt to a processor executing a low-level program, an interrupt control device 10 transmits a low-level request as shown in FIG. 1a. A system is used in which a processor 11 running a priority program is detected and an interrupt request is transmitted.

According to this method, N processors 11 to 1
In order to detect the processor 11 that is executing the program with the lowest rank among the A dedicated signal line is required to transmit the order of the program being executed from ~1N to the interrupt control device 10. Furthermore, if the rankings are sequentially compared using one comparison circuit, it will take a long time for detection. Furthermore, using this method,
When the interrupt control device 10 fails, the entire device becomes inoperable. Further, in order to obtain high reliability, it is also necessary to duplicate the interrupt control device 10.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a data processing device that can generate an interrupt to a processor running a low-level program without using an independent interrupt control device.

The apparatus of the present invention is a data processing apparatus having a plurality of program control apparatuses that execute programs according to program execution priorities and accept interrupts of a higher priority than the program execution order, in which each of the program control apparatuses executes a program. holding means for holding a program rank value representing the execution priority of a program therein; generating means for generating a subdivision rank value for adding a subdivision rank to the execution priority; and sending and receiving information between the program control device. When performing the above, the held program order position and the subdivision rank value are transmitted and received via a communication channel, and the rank value to be transmitted is compared with the transmitted and received rank value, and it is detected that the said rank value is the lowest rank. The present invention is characterized by comprising a detection means.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1b shows a block diagram of the data processing apparatus of the present invention. Interrupt requests are sent to each processor 11~
1N directly.

FIGS. 2a to 2c are diagrams showing a method of expressing priorities. In the following, the priority order is expressed as a binary value, with the number "0" being the upper limit, and the larger the number, the lower the order. Data representing a numerical value is composed of multiple bits. FIG. 2a shows program order data representing the execution priority of programs. Each processor 1 shown in FIG.
1 to 1N hold this program ranking data, and by comparing this data among the processors 11 to 1N, the processor 11 having the largest value, that is, the processor 11 that is executing the lowest ranking program, can be selected. . However, if two or more processors are executing programs of the same rank, only one processor cannot be selected. Therefore, in order to select one processor, data obtained by adding subdivision ranking data to program ranking data is used as shown in FIG. 2c. In the ranking data shown in FIG. 2c, subdivision ranking data is arranged at bit positions lower than the least significant bit of the program ranking data, so that the same program ranking can be further subdivided. 1st b
By assigning unique subdivision data to each processor in the diagram, one processor can always be selected.

FIG. 3 shows the detailed configuration of each processor shown in FIG. 1b. In FIG. 3, reference numeral 1 is a register that holds program order data. Reference numeral 2 is a circuit for generating subdivision rank data, and a simple method for generating such data is a circuit using a switch. Data from register 1 and circuit 2 is supplied to processor selection circuit 3 in the arrangement shown in FIG. 2c. The communication path 101 is a means for connecting the circuits 3 in all processors, and is a bidirectional communication path 101. Data sent from the processor selection circuit 3 of one processor is transmitted to all other processors via the communication path 101. The processor selection circuit 3 transmits the data shown in FIG. 2c supplied from the register 1 and the generation circuit 2 to other processors via the communication path 101, receives data from other processors, and selects the data to be transmitted. This circuit detects that its own processor is in a lower rank than other processors by comparing the received data with the received data.

FIG. 4 is a diagram showing a detailed configuration of the processor selection circuit 3. In FIG. 4, the signal line 30
Lines 1, 302 and 303 are connected to the communication path 101 in FIG. 3, and signal lines 311, 312 and 313 are lines for transmitting data supplied from the register 1 and generation circuit 2 in FIG. The output of the AND circuit 40 is connected to the signal line 102 in FIG. Drive circuits 33, 34, and 35 are circuits that invert the outputs of AND circuits 30, 31, and 32, respectively, and send them out. Drive circuit 33 corresponds to the most significant bit of the sending data, and drive circuit 35 corresponds to the least significant bit. . If the most significant bit of the data to be sent is logic “1”, the drive circuit 33
sends out the logical value “0” of negative logical value, and the OR circuit 3
The output of 6 becomes logic "1" and enables data transmission of the lower bit. If the most significant bit of the data to be sent is logic “0”, the drive circuit 3
3 sends out a logic "1" with a negative logic value, but at this time, if the drive circuit 33 of the other processor sends out a logic "0" with a negative logic value, the data on the signal line 301 will be a negative logic value. The logic becomes "0" and the output of the OR circuit 36 becomes logic "0", inhibiting the transmission of lower bit data. By performing this operation for each data bit, the data with the maximum value among the data to be sent from all processors is transferred to the signal line 3.
01, 302 and 303. At this time, the outputs of the OR circuits 36, 37, and 38 of only the processor that is sending out the data of the maximum value all become logic "1", and the output of the AND circuit 40 becomes logic "1". The output of the AND circuit 40 becomes logic "1" only in one processor, and the output of the AND circuit 40 becomes logic "1".
Since this means that the processor has been selected, the processor responds to the interrupt request. That is, when the output of the AND circuit 40 becomes logic "1", the signal line 1 in FIG.
In response to the signal 02, the AND circuit 6 sends the output of the comparison circuit 5 to the signal line 103. The comparison circuit 5 compares the data supplied from the register 1, that is, the program order data, and the interrupt order data given via the communication path 104, and when the interrupt order data is smaller than the program order data, that is,
When the interrupt priority is higher than the program priority, an output "1" is sent to the AND circuit 6. The output of the AND circuit 6 indicates the start of an interrupt operation. Although FIG. 4 shows an example in which the rank data consists of 3 bits, the number of bits can be easily increased.

In the present invention, a single processor executing a low-rank program can respond to an interrupt request without using a dedicated interrupt control device by comparing the combination of program ranking and subdivision ranking between processors. It has the effect of being able to respond.

[Brief explanation of the drawing]

Fig. 1a shows a conventional data processing device using a dedicated interrupt control device, Fig. 1b shows a data processing device of the present invention, and Figs. 2a to 2c show a method for determining priorities. FIG. 3, and FIG. 4 are diagrams showing an embodiment of the present invention. 3 and 4, 1...Register, 2...Subdivision rank data generation circuit, 3...Processor selection circuit, 5...Comparator, 6, 30, 3
1, 32, 40... AND circuit, 33, 34 and 35... Drive circuit, 36, 37 and 38...
OR circuit.

Claims (1)

[Scope of Claims] 1. A data processing device having a plurality of program control devices that execute programs according to program execution priorities and accept interrupts of a higher priority than the program being executed, each of the program control devices including: holding means for holding a program rank value representing the execution priority of the program being executed; generating means for generating a subdivision rank value for adding a subdivision rank to the execution priority; and information exchange between the program control devices. When transmitting and receiving, the held program rank value and the subdivision rank value are transmitted and received via a communication path, and the rank value to be transmitted is compared with the received rank value, and it is detected that the rank value is the lowest rank. What is claimed is: 1. A data processing device comprising a detection means for detecting.