JPH0129637Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a microprocessor analyzer, and more specifically, to an application device using a microprocessor configured to perform memory management according to a status signal of the microprocessor. A microprocessor analyzer that has the function of accessing the memory of a target system by operating the target system as a target system according to the microprocessor analyzer's active program as necessary, and reading and rewriting the contents of that memory. It is.

Some types of microprocessors are configured so that memory management can be performed using microprocessor status signals. In application equipment using a microprocessor that performs such memory management, for example, program access or data access is selectively set according to a status signal, and the memory is programmed using the same address according to the output of the status signal. The code area or data area will be accessed. This has resulted in substantial memory expansion.

On the other hand, a type of microprocessor analyzer has a passive trace function that displays the operation history of the target processor on a CRT without affecting the operation of the microprocessor (hereinafter referred to as the target processor) that makes up the target system. Then, it actively intervenes in the operation of the target processor, switches the target processor bus to the active program provided in the microprocessor analyzer, and executes the active program to read the contents of the target processor's internal registers and memory. Some devices have an active function that reads out the data and displays it on the CRT.

By the way, such conventional microprocessor analyzers do not take into account the active function operations of the target processor, which is configured to perform memory management according to the status signals mentioned above, and the Reading and rewriting operations could only access the data area, but not the program code area.

The present invention solves these drawbacks, and includes a pseudo-status signal generation circuit that generates pseudo-status signals in a microprocessor analyzer that performs active function operations, and a pseudo-status signal generation circuit that generates pseudo-status signals from the microprocessor of the target system. a status signal switching circuit that selectively adds a pseudo status signal sent from the signal or pseudo status signal generating circuit to the memory of the target system to be accessed; and an active circuit that controls the operation of the pseudo status signal generating circuit and the status signal switching circuit. It is equipped with a status control circuit.

Hereinafter, it will be explained in detail using the drawings.

The drawing is a block diagram of the main parts of an embodiment of the present invention, where MPA is a microprocessor analyzer according to the present invention, TS is a target system,
B1 to B4 are buses.

In MPA, ACPU is a processor, CRT is a cathode ray tube used as a display, and CRTC is a CRT.
Controller, KBD is keyboard, KIF is KBD
interface, ROM is a read-only memory that stores fixed information such as programs, RAM is a random access memory that temporarily stores variable data such as calculation data, BCTL is a bus control circuit,
BDMY is bidirectional memory, AROM is read-only memory where active programs are stored,
ACTL is active status control circuit, DSG
is a pseudo status signal generation circuit, SSW is a status signal switching circuit, and BMPX is a bus multiplexer. In TS, TCPU is a processor,
PCA is the program code area and DTA is the data area.

In such a configuration, bus B1 connects processor TCPU and bus multiplexer BMPX, and bus B2 connects bus multiplexer BMPX, program code area PCA, and data area DT.
and bus B3 is a bus multiplexer.
Connect BMPX and bus control circuit BCTL, active status control circuit ACTL, bidirectional memory BDMY and read-only memory AROM, and connect bus B4
Processor ACPU and bus control circuit BCTL.Bidirectional memory BDMY.CRT controller CRTC.KBD
Interface KIF. Connects read-only memory ROM and random access memory RAM. Note that the bus control circuit BCTL sends a control signal Sc ₁ to the bus multiplexer BMPX, and the active status control circuit ACTL sends a control signal Sc ₂ to the pseudo status signal generation circuit DSG and the status signal switching circuit SSW. A pseudo status signal Sds is sent from the signal generation circuit DSG to the status signal switching circuit SSW. In addition, a status signal switching circuit is sent from the processor TCPU of the target system TS.
SSTW.A status signal Ss is sent to the bidirectional memory BDMY and read-only memory AROM, and a pseudo status signal Sds or status signal Ss is sent from the status signal switching circuit SSW to the program code area PCA and data area DTA.

The operation of the device configured in this way will be explained.

The operator operates the keyboard KBD to
The area to be accessed (in this embodiment, the program code area PCA or the data area DTA) is specified and input into the microprocessor analyzer MPA from within the memory area of the target system TS. The processor ACPU of the microprocessor analyzer MPA controls the bus control circuit BCTL and active status control circuit according to this specified input.
Set conditions for ACTL. For example, when the program code area PCA is accessed, the pseudo status signal generating circuit DSG sends a pseudo status signal Sd of "0" level to the status signal switching circuit SSW. Then, the status signal switching circuit SSW sends out this "0" level pseudo status signal Sd to each part. This results in
The program code area PCA will be accessed according to the active program stored in the read-only memory AROM, regardless of the status signal Ss of the processor TCPU of the target system TS. In addition, the bus control circuit BCTL
synchronizes with these series of operations, connects bus B1 to B2.
Alternatively, the control signal Sc ₁ is sent to the bus multiplexer BMPX so as to be connected to the bus multiplexer BMPX. Here, the bidirectional memory BDMY is used as a mailbox for data transmission between the target system TS and the microprocessor analyzer MPM.

According to this configuration, for a target system using a microprocessor configured to perform memory management using status signals,
A desired memory area can be accessed by performing an active function operation.

In the above embodiment, an example was shown in which only two types of status, data and programs, are distinguished, but it goes without saying that the same configuration can be made even when three or more types are distinguished.

As explained above, according to the present invention, it is possible to realize a microprocessor analyzer that is effective for debugging a target system using a microprocessor configured to perform memory management using status signals, and has practical effects. big.

[Brief explanation of drawings]

The drawing is a block diagram of essential parts showing an embodiment of the present invention. MPA……Microprocessor analyzer, TS
...Target system, B1-B4...Bus,
ACPU...processor, CRT...branch tube,
CRTC...CRT controller, KBD...keyboard, KIF...KBD interface, ROM...
Read-only memory, RAM...random access memory, BCTL...bus control circuit, BDMY...
…bidirectional memory, AROM…read-only memory, ACTL…active status control circuit,
DSG...Pseudo status signal generation circuit, SSW...
…Status signal switching circuit, BMPX…Bus multiplexer, TCPU…Processor, PCA…
...Program code area, DTA...data area.

Claims (1)

[Scope of utility model registration request] The target system is an application device using a microprocessor configured to perform memory management according to the status signal of the microprocessor, and this target system is operated according to the active program of the microprocessor analyzer as necessary. A microprocessor analyzer that has the function of accessing the target system's memory and reading or rewriting its contents, which includes a pseudo status signal generation circuit that generates a pseudo status signal and a pseudo status signal that is sent from the target system's microprocessor. A status signal switching circuit that selectively adds a pseudo status signal sent from the status signal or pseudo status signal generating circuit to the memory of the target system to be accessed, and controls the operation of the pseudo status signal generating circuit and the status signal switching circuit. A microprocessor analyzer consisting of an active status control circuit.