JPH0713815B2 - Bus converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a bus conversion device between systems of a data processing system having a bus conversion means between a host system and a connection system, and a bus operation having a relatively long bus occupation time. (A bus operation is a bus operation by memory access such as read and write and interrupt processing) is converted into a bus operation with a relatively short bus occupation time, thereby releasing the bus early and improving the bus performance. SUMMARY OF THE INVENTION The present invention is directed to a bus conversion device between systems in a data processing system in which a host system and a connection system are connected by a bus conversion means, wherein the bus conversion means includes the connection system for each entry. Add with at least one bit indicating the form of bus operation to the side And a control logic for instructing a bus operation to the connection system based on a mode of the bus operation from the host system side when accessing the connection system side, At the time of access from the host system side, an arbitrary bus operation can be instructed to the connection system side based on the instruction of the bit.

[Industrial application field]

The present invention relates to a bus conversion device in a bus conversion, and more particularly, in a data processing system connected to a host system by a bus conversion means, a bus conversion of a memory having a lock byte function for consistent access from both systems. Regarding the device.

[Problems to be Solved by Prior Art and Invention]

A data processing system including a bus conversion device for the purpose of supporting the system bus B between the system bus A of the host system (A) and the system bus B of the connection system (B) is already known. In this case, the system bus B is generally called a distribution bus, for example, VME-bus or Mu.
The lti-bus and the like are known as standardized buses (standard buses). Although a plurality of memories and I / Os are connected to the system bus B, a shared memory accessible from both the systems A and B is usually provided with a lock byte in a part of the memory area. Since both the host system A and the connection system B access without contradiction, it indicates whether access to the shared memory is impossible or not depending on whether the most significant bit of the lock byte is "0" or "1". ing. Therefore, the other device determines whether or not the access to the shared memory is possible at present by looking at the state of the lock byte. Normally, if the lock byte is "1", it indicates that the shared memory area is dedicated to the processor connected to the system bus A or B.

On the other hand, when accessing the lock byte of the memory connected to the bus A from the host system A side, RMW is generally used.
(Read-Modify-Write) cycle is used. The RMW cycle is to perform read / write access with one bus operation. When multiple processors try to monopolize the shared memory for a certain period, this bus cycle is used.
Access to the lock byte, determine availability, and if available (most significant bit is "0"), set the most significant bit to "1" in the following write cycle to inform other processors of occupancy. It is a squeal. When releasing the shared memory, unconditionally write "0" to the lock byte.
This RMW cycle is also used between the system bus A and the bus converter and between the bus converter and the system bus B. Therefore, during this period, any system bus is exclusively used for the access, and the use of other I / O and the like is excluded.

However, in such a bus cycle, the bus occupation time becomes very long. That is, since the RMW is a form in which the read cycle and the write cycle are combined in order to prevent an interrupt from another device, it simply requires twice as many cycles as the normal read-only cycle or write-only cycle. is doing. In this way, in the RMW cycle, both the system bus A and the system bus B occupy the bus during this period, and the bus use of other devices is excluded during this period, which impedes the speedup of the entire system. In addition, a control means for RMW cycle is required in the bus converter, a dedicated bus signal is required, and if one bus does not support bus operations such as RMW cycle, the system configuration and There are problems such as limited functions.

An object of the present invention is to quickly release a bus by converting a bus operation having a relatively long bus occupation time, such as an RMW cycle, into a bus operation having a relatively short bus occupation time as an access mode in a bus converter. Another object is to improve the bus performance and to provide a means for locking the shared memory of a plurality of processors efficiently connected to different buses with a small quantity.

[Means and Actions for Solving Problems]

FIG. 1 is a basic configuration diagram of the present invention. In the figure, a bus converter C is connected between a system bus A on the host system A side and a system bus B on the connection system B side, and in the bus converter C, address conversion for a memory having a lock byte is performed by software. An address translation map 1 that has been set, an address translation logic 2 that handles the logic, and a bus operation control logic 3 that controls the operation between systems are provided. The address translation map 1 is divided into n entries, and each entry is a bus operation instruction bit (or bit group).
It consists of B-OP and address bits. The bus operation instruction bit B-OP may be the beginning or the end of the address as its position, and has, for example, "1" for instructing the RMW cycle. Indicator bit B
If OP is "1", the system bus B is instructed to perform the RMW cycle. If the instruction bit B-OP is "0", the system bus B is subjected to a normal read cycle.

That is, when the system A accesses the system B, the address translation logic 2 executes the address translation, and at the same time, the bus operation control logic 3 determines the type of the instruction bit B-OP and the bus operation (for example, read or write) of the system A. Judge and execute the same bus operation for system B as for system A, or RM
Controls whether special bus operations like W are performed. For example, as described above, when the instruction bit B-OP is "0", the write access to the system B is directly written and the read access is directly read. When the instruction bit B-OP is "1", the system B
The write access to is directly written, but the read access is instructed to execute the RMW cycle. In this case, the system B can access the system A or the systems A and B can access each other in the same manner as described above.

The setting of whether the instruction bit B-OP is "1" or "0" in each entry is performed by setting the instruction bit B-OP of the entry having the address corresponding to the address of the lock byte at system startup. If set to "1", the RMW cycle will be possible. That is, a lock byte is provided in order to access the shared memory that can be accessed by both the system A and the system B without contradiction, but the instruction bit B-OP of the entry of the address corresponding to the lock byte is set to "1". If it is set to ", be sure to specify the address of the lock byte to RM the shared memory.
W cycle can be executed. In addition, by returning the data read in the read section of the RMW cycle of the other bus in response to the read access from one bus, the processor that executed the read access has the most significant bit of the read data as "0". When the bus converter
It is possible to know that the write part of the RMW cycle is executed and "1" is written in the most significant bit of the lock byte, that is, the shared memory is locked.

〔Example〕

FIG. 2 is a block diagram of the essential parts of one embodiment of the present invention. In the figure, the case where the system A accesses the system B is shown, and it is assumed that the memory M having a lock byte is connected to the system bus B. As described above, when the instruction bit B-OP is "0", the bus operation is not changed, and when it is the instruction bit B-OP, the RMW cycle is executed for the system B according to the bus operation type of the system A.

In this embodiment, if the instruction bit B-OP is "1" at the time of write access as the mode of access and the RMW cycle is executed, the instruction bit B-OP of the predetermined entry in the address translation map is "1", When the access from the CPU is a write access (WRITE), the bus conversion device C immediately returns a response signal S to the system A, and at the same time, to the system B via the bus operation control logic 3, an RMW cycle (RMW cycle). ) Is executed. Whether or not the data set for the lock byte memory M has been completed is prepared in the bus operation control logic 3 by providing a register REG accessible from the system A and displayed in this register. System A (READ) this register REG
By doing so, the result of RMW is determined.

FIG. 3 is a block diagram of the essential parts of another embodiment of the present invention. In this embodiment, two entries are prepared for one address in the address translation map 1 for the memory having the lock byte, and one instruction bit B-OP is set to "0" and the other is set to "1". . Therefore, when viewed from the system A, the address of the lock byte memory is prepared in the address conversion map for read / write and RMW. Prepared in this way, normal read / write access (R / W) from the system A is performed by the instruction bit B-OP.
Can access the entry of "0" to perform normal read / write to system B, while RMW
In order to perform the operation, the entry having the instruction bit B-OP of "1" is accessed and read-accessed to the system B
Perform RMW cycle. In this case, the bus conversion device C transfers the read data of the lock byte to A, terminates the bus cycle of the system A, and simultaneously sets the lock byte. If the lock byte of the read data is not set, the system A determines that it can set it.

The address conversion logic 2 is a normally used conversion logic, and is composed of a RAM, and its upper bits are used as RAM addresses and its lower bits are used as addresses to the system B. Further, the bus operation control logic 3 is a logic which takes in the instruction bit B-OP from the system A, determines whether the access is a read or a write and determines the bus operation to the system B.

〔The invention's effect〕

As described above, according to the present invention, a bus operation having a relatively long bus occupation time, such as an RMW cycle, is converted into a bus operation having a relatively short bus occupation time to release the bus early. It is possible to improve the bus performance, eliminate the need for a bus control circuit and a bus signal for a special bus operation, and further, for example, for a bus operation that is in the system B but not in the system A. Indication bit B-OP
It is also possible to support by setting.

[Brief description of drawings]

 FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of a main part of an embodiment of the present invention, and FIG. 3 is a configuration diagram of a main part of another embodiment of the present invention. (Explanation of symbols) A, B ... System bus, C ... Bus conversion device, 1 ... Address conversion map, 2 ... Address conversion logic, 3 ... Bus operation control logic.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-56-11554 (JP, A) JP-A-59-178522 (JP, A) JP-A-60-169961 (JP, A) JP-A-59- 178522 (JP, A) JP 62-282351 (JP, A) JP 60-134953 (JP, A)

Claims (1)

[Claims] 1. A bus conversion device for connecting a bus of a host system and a bus of a connection system, at least 1 for each entry for instructing a mode of bus operation such as memory access to the connection system side.
An address translation map (1) having one operation mode instruction bit (B-OP), and an inter-bus map based on an address in a corresponding entry of the address translation map when the host system accesses the connection system side. An address translation logic (2) for performing address translation of the host system, based on an operation mode instruction bit in a corresponding entry of the address translation map when the host system accesses the connection system side. A control logic (3) for converting a bus operation into a bus operation on the connection system side is provided, and when the host system side accesses the connection system side, the operation is performed for a corresponding address on the connection system side. Optional on the connection system side based on the mode indication bit Bus conversion device is characterized in that so as to enable direct the bus operation.