JPS62106667A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a junction capacitance and improve device characteristics by a method wherein two polycrystalline silicon layers are formed and lead electrodes with side walls are formed for source-drain layers by reactive ion etching. CONSTITUTION:An oxide film 2 and a nitride film 3 for selective oxidization are formed on a silicon substrate 1. The nitride film 3 is removed except the part on an active region 4 and field oxide films 5 are formed by heat oxidization. The remaining nitride film 3 is removed and the 1st polycrystalline silicon layer 6 and an insulating film 7 are successively formed. The insulating film 7 and a 1st polycrystalline silicon layer 6 are removed except the arts where lead electrodes are formed and the lead electrodes 61 are formed. A 2nd polycrystalline silicon layer is formed over the whole surface and an impurity is introduced. The 2nd polycrystalline silicon layer is removed to form side walls 81. A gate oxide film 9 and source-drain layers 10 are formed by oxidization. A gate electrode 11 is formed and a layer insulating film 12 is applied and electrode lead aperture 13 are drilled to form source-drain electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing semiconductor devices, particularly MO3 type transistors.

(Prior Art) A conventional manufacturing method will be explained step by step with reference to FIGS. 3 fat to +e+.

First, an oxide film 2 and a nitride film 3 for selective oxidation are formed on the silicon substrate 1 as shown in FIG.
As shown in bl, a field oxidation layer 5 is formed in a portion other than the active region 4. Next, the entire surface is covered with a polysilicon layer, and the polysilicon other than the gate 1 area is removed.
A gate electric cover 31 is formed as shown in Figure +C). This and s
-1? In order to lower the electrical resistance of the silico, it is doped with impurities such as phosphorus in advance.

Subsequently, impurities are introduced into the source/drain region by ion implantation or the like to form the source/drain layer 32 by approximately 0.5 μm.
After forming the insulating film 33 to a depth of m (5 m), an insulating film 33 is formed by, for example, the CVD method as shown in FIG. 3F and 11.

Next, as shown in FIG. 3(e), an electrode extraction hole 34 is opened in the source/drain region, and a north/drain electrode 35 is formed to complete a MOS type 11-lanon star.

FIG. 4 is a pattern layout diagram of a MOS type transistor manufactured by the above-mentioned conventional method. In this figure, the active inner margin (space + phytomask alignment margin) of the electrode extraction hole 34 is W4, the size W5 of the electrode extraction hole 34, and the margin between the gate 31 and the electrode extraction hole 34 (spacer photomask alignment margin). W 6, ge~! - length is W2
For example, if the minimum pattern width is 2 μm, the minimum pattern spacing is 1 μm, and the photomask alignment margin is 1 μm, then the source, dot, 2-inch length (W3X2) and active length (Wl
) is the source dray J length: W3X2= (W4+W5
+W6)X2= (1+1+2+1+1)x2 -12 (μm) Active length: Wl = (W4+W5+W6)x
2+W2=12-+-2=14 Cμm).

(Problems to be Solved by the Invention) As described above, if the device is formed by the conventional method, the source dot 1. - The length of the in in the gate length direction is required to be approximately 12 μm based on current patterning requirements, and in order to further reduce this, it will be necessary to improve the patterning ff degree and reduce the mask alignment margin, and technology It can be said that it is extremely difficult.

The present invention provides a manufacturing method for reducing the size of a device without placing any burden on the patterning precision mask alignment margin, and mainly reduces the impurity diffusion regions that become the source and drain to a large extent, thereby increasing the junction capacitance. The purpose is to improve device characteristics by reducing the

(Means for solving the problem) In the method for manufacturing a semiconductor device of the present invention, the sidewall is formed by forming two polysilicon layers and etching by RIE method. 6. (Function) In the method of the present invention, an electrode is drawn out from the north drain region to the field oxide film layer in an MO3 type transistor. At this time, the source/drain regions are widened by connecting the end portion of the first polysilicon layer in the active region and the surface of the silicon substrate in the active region, which will become the source/drain regions, with a sidewall formed of the second polysilicon layer. The effective active surface S (gate region + source/drain region)
is determined almost exclusively by the gate area.

(Example) The manufacturing method of the present invention will be explained in order of steps with reference to FIG. 1 ta+ to if).

First, as shown in FIG. 1, an oxide film 2 and a nitride film 3 for selective oxidation are sequentially formed on a silicon substrate 1. Next, Figure 1 (
As shown in bl, the nitride film 3 other than the active region 4 is removed and a field oxide film 5 is formed by thermal oxidation. Subsequently, as shown in FIG. , doping with impurities or silicidation (T i
-5i, W-3i.

Mo-3i etc.). Next, as shown in Figure 1 (dl),
The insulating film 7 and the first polysilicon layer 6 other than the portions that will become the source/drain extraction electrodes 61 are sequentially removed by RIE to form the extraction electrodes 61. At this time, the extraction electrode 61 only needs to be in contact with the active region 4 to the extent that there is room for photomask alignment.

Further, the entire surface is covered with a second polysilicon layer 8 (about 0.5 μm thick), and impurities forming a north drain layer are introduced into the second polysilicon layer 8 by ion implantation or the like. Next, as shown in FIG.
A sidewall 81 of the second polysilicon remains on the end side wall of the first polysilicon that remains as a polysilicon. and,
Gate oxide film 9 and source/drain layer 1 are removed by oxidation.
0 is formed. Next, as shown in FIG. 1 (FIG. 1, the electrode 11 is formed so as to overlap a part of the extraction electrode 61 including the sidewall 81), and after the interlayer insulating film 12 is deposited, the electrode extraction hole 13 is Open a hole and source/drain voltage 1
The grinding wheels 14 are respectively formed to obtain MO3 type tow/disk.

FIG. 2 is a pattern layout diagram of an MO3 type transistor manufactured by the above-described method of the present invention.

In this figure, the source/drain junction region (shaded area)
Since W3 is formed of the polysilicon sidewall 81, it has a length of about 0.5 μm, and the source/drain electrode W3X2) can be formed with a length of about 1 μm.

(Effects of the Invention) The effects obtained by the method of the present invention will be compared with those of the conventional method, and will be explained below.
For example, if the length I- in the gate width direction is 5 μm, the fourth
The bonding area (shaded area) required by the conventional method in the figure is 12
X5=60 (μm'), but in the method of the present invention shown in FIG. 2, lX5=5 (μm'), achieving an extremely large reduction. This reduction in the source/drain junction region reduces the junction capacitance, which greatly contributes to improving the operating characteristics of the semiconductor device.

Furthermore, in the present invention, since the doped polysilicon method is applied to lead out the electrode from the J layer, diffusion of the electrode material, which is a problem when leading out the electrode from a shallow junction, The advantageous effects include the fact that there is no need to worry about the resulting junction 'I - current (so-called Ano+=E spike).

[Brief explanation of drawings]

Figures 1 (fat to if) are cross-sectional views sequentially showing the manufacturing process of the present invention, Figure 2 is a layout diagram of a semiconductor element manufactured by the method of the present invention, and Figures 3 fal to fel are cross-sectional views sequentially showing the conventional manufacturing process. FIG. 4 is a layout diagram of a semiconductor device manufactured by a conventional method. 1-Silicon substrate, 2...Oxide film, 3...Nitride film, 4
Active region, 5. Field oxide film, 6° first polysilicon layer, 61. Leading electrode, 7. Insulating film, 8
・・Second polysilicon layer, 81 Sa (wall, 9・
・Gate oxide film, 10. Source/drain layer, 11 Gate electrode, 12 ・Interlayer insulating film, 13. Electrode extraction hole, 14. Source/drain electrode, 31 Gate electrode,
32 source/drain layer, 33 insulating film, 34 electrode extraction hole, 35 source/drain electrode. 3? Fig. 1: Cross-sectional view showing suppuration)

Claims (1)

[Claims] When manufacturing a semiconductor device, (a) after sequentially depositing an oxide film and a nitride film for selective oxidation on the surface of a semiconductor substrate, and sequentially removing the nitride film and oxide film in areas other than the active area, (b) removing the nitride film remaining on the active region and sequentially forming a first polysilicon layer and an insulating film; (c) sequentially removing the insulating film, the first polysilicon layer, and the oxide film for selective oxidation except for the part extending over the field oxide film from a part of the field oxide film by RIE (reactive ion etching); After forming a second polysilicon layer on the entire surface and introducing impurities only into this second polysilicon layer, this second polysilicon layer is removed by the layer thickness by RIE method to form an extraction electrode having sidewalls. (d) After sequentially forming a source/drain layer, a gate oxide film, and a gate electrode, a step of depositing an interlayer insulating film on the entire surface; (e) forming an electrode extraction hole at a predetermined position of the extraction electrode; A method for manufacturing a semiconductor device, comprising sequentially performing the steps of opening holes and forming source/drain electrodes.