JPS62104129A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62104129A JPS62104129A JP60244411A JP24441185A JPS62104129A JP S62104129 A JPS62104129 A JP S62104129A JP 60244411 A JP60244411 A JP 60244411A JP 24441185 A JP24441185 A JP 24441185A JP S62104129 A JPS62104129 A JP S62104129A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- semiconductor chip
- hole
- wafer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔発明の概要〕
本発明は、半導体チップをパッケージ内に実装する際に
、パッケージ側のリードにワイヤボンディングするため
のバンドを上記半導体チップの表裏両面に形成して、半
導体チップの表面のみでなく、裏面からもワイヤボンデ
ィングを可能にすることにより、高集積ディバイスの信
号線の取出しを容易にしたものである。[Detailed Description of the Invention] [Summary of the Invention] The present invention provides a method for mounting a semiconductor chip in a package by forming bands on both the front and back sides of the semiconductor chip for wire bonding to leads on the package side. By enabling wire bonding not only from the front surface of the semiconductor chip but also from the back surface, signal lines from highly integrated devices can be easily taken out.
本発明は、半導体チップをパッケージ内に実装してなる
半導体装置及びその製造方法に係り、特に実装時におけ
るワイヤボンディングの構成及び方法の改良に関する。The present invention relates to a semiconductor device in which a semiconductor chip is mounted in a package and a method for manufacturing the same, and particularly to improvements in the structure and method of wire bonding during mounting.
従来の半導体装置におけるボンディングする際の組立状
態を第４図（ａｌ及び（ｂｌに示す。同図（ｂｌは同図
ｆａ）のＡ−Ａ断面図である。FIG. 4 shows an assembled state of a conventional semiconductor device when bonding is performed.
同各図において、半導体チップ３の表面には複数のパッ
ド（不図示）が形成されており、これらの各パッドとリ
ードフレーム２の各リード２ａとが、ボンディングによ
りワイヤ４によって接続されている。In each figure, a plurality of pads (not shown) are formed on the surface of a semiconductor chip 3, and each of these pads and each lead 2a of a lead frame 2 are connected by wires 4 by bonding.
このような半導体装置を製造するには、まず。To manufacture such a semiconductor device, first.
例えばセラミックからなる基板１上に櫛歯型に形成され
たリードフレーム２を載置し、さらに半導体チップ３を
リードフレーム２，２間でかつ基板１の上に載置して、
焼結等によりリードフレーム２．２と半導体チップ３を
基板１に埋込み固定する。次に、ワイヤ４を半導体チッ
プ３表面の上記パッドとリードフレーム２のリード２ａ
間にボンディングした後に、不図示のパッケージを覆せ
てから切断線５でリードフレームの共通部分２ｂを切断
することにより、半導体装置を構成する。For example, a comb-shaped lead frame 2 is placed on a substrate 1 made of ceramic, and a semiconductor chip 3 is placed between the lead frames 2 and on the substrate 1.
The lead frame 2.2 and the semiconductor chip 3 are embedded and fixed in the substrate 1 by sintering or the like. Next, the wire 4 is connected to the pad on the surface of the semiconductor chip 3 and the lead 2a of the lead frame 2.
After bonding between them, the package (not shown) is turned over and the common portion 2b of the lead frame is cut along the cutting line 5, thereby constructing a semiconductor device.
一般に１通常のＩＣチップでは上述したようなパッドの
数が１００〜２００個必要であり、また超ＬＳＩのチッ
プではそのバッド数が４００〜５００１固と更に多（必
要になる。すると、半導体チップ３の片面からのみワイ
ヤ４をボンディングする上記従来の半導体装置では、パ
ッドの形成箇所がチップ３の表面にのみ限定されるため
、そのボンディングの際にワイヤ同士が交叉したり、あ
るいは互いに近接しすぎて、極端な場合には接触してし
まう等の問題を生じる場合があった。In general, a normal IC chip requires 100 to 200 pads as described above, and a VLSI chip requires an even larger number of pads (400 to 5001). In the conventional semiconductor device described above, in which the wires 4 are bonded only from one side of the chip 3, the pads are formed only on the surface of the chip 3, so the wires may cross each other or be too close to each other during bonding. In extreme cases, problems such as contact may occur.
本発明は、上記従来の問題点に鑑み、ＬＳＩ。In view of the above-mentioned conventional problems, the present invention is directed to an LSI.
超ＬＳＩ等の高集積ディバイスにおいても、上記のよう
なワイヤの交叉あるいは接触がなく、容易に信号線を取
出すことのできる半導体装置およびその製造方法を提供
することを目的とする。It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which signal lines can be easily taken out even in highly integrated devices such as VLSIs, without the above-mentioned crossing or contact of wires.
上記目的を達成するために３本発明に係る半導体装置は
、半導体チップの表裏両面に形成されたパッドと、パッ
ケージに固定されたリードとが。To achieve the above object, a semiconductor device according to the present invention includes pads formed on both the front and back surfaces of a semiconductor chip, and leads fixed to a package.
上記表裏両面からそれぞれワイヤボンディングされる構
成としたものである。The structure is such that wire bonding is performed from both the front and back surfaces.
また、その製造方法は、半導体チップとなるウェハーに
対して表裏にＮ通する透孔を形成する工程と、上記ウェ
ハーの表面にバンドを形成し、また裏面にも上記の透孔
を介してパッドを形成する工程と、これらの各バンドと
リードとをそれぞれワイヤボンディングする工程と、こ
のワイヤボンディングされたウェハーをパッケージする
工程とからなっている。The manufacturing method also includes a step of forming N through holes on the front and back sides of the wafer that will become the semiconductor chip, forming a band on the front side of the wafer, and also forming a band on the back side of the wafer through the through holes. , a step of wire-bonding these bands and leads, and a step of packaging the wire-bonded wafer.
本発明に係る半導体装置は、パッドが半導体チップの表
面のみならず裏面にも形成されている。In the semiconductor device according to the present invention, pads are formed not only on the front surface but also on the back surface of the semiconductor chip.
そのため、従来表面にのみ形成されていたパッドが表裏
両面に分散されたことになり１表裏各面におけるパッド
数は減少する。序って９両部会体のパッド数が増加して
も、各面におけるパッドとパッドとの間隔を従来よりも
相当に広くとることができ、ボンディング時にワイヤ同
士が交叉したり。Therefore, the pads that were conventionally formed only on the front surface are now distributed on both the front and back surfaces, reducing the number of pads on each surface. Even if the number of pads in the 9-side assembly increases, the spacing between the pads on each side can be made considerably wider than in the past, which prevents wires from crossing each other during bonding.
接触したりすることがなくなる。There will be no more contact.
また、その製造方法として、半導体チップに対して表裏
に貫通する透孔を形成することによって。Further, as a manufacturing method thereof, a through hole is formed that penetrates the semiconductor chip from the front and back sides.
表面だけでなく裏面にも容易にパッドを形成できるよう
にしている。従って２表面に形成されたバンドと、透孔
を介して裏面に形成されたバ・シトとが存在することに
なり、上述したように各面におけるパッドの間隔を広く
とることができるため。Pads can be easily formed not only on the front side but also on the back side. Therefore, there is a band formed on two surfaces and a base formed on the back surface through the through hole, and as described above, the spacing between the pads on each surface can be widened.
その後のボンディング工程を非常に容易にしている。This makes the subsequent bonding process very easy.
以下１本発明の実施例について１図面を参照しながら説
明する。An embodiment of the present invention will be described below with reference to one drawing.
第１図は１本発明に係る半導体装置の一実施例を示す断
面図である。同図において、半導体チップ１４の表面及
び裏面には、後に第２図によって詳述するが、それぞれ
複数のパッドが形成されている。これら表面、裏面の各
パッドと、側方に突出したり一ド１３ｄの各々とが、そ
れぞれワイヤ１５ａ、１５ｂによってボンディングされ
ている。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In the figure, a plurality of pads are formed on the front and back surfaces of the semiconductor chip 14, respectively, as will be explained in detail with reference to FIG. 2 later. The pads on the front and back surfaces and the laterally protruding pads 13d are bonded by wires 15a and 15b, respectively.
更に、これらの半導体チップ１４．リード１３ｄ及びワ
イヤ１５ａ、１５ｂは、パッケージ１６ａ。Furthermore, these semiconductor chips 14. The lead 13d and wires 15a, 15b are included in the package 16a.
１６ｂによって上下方向から包むように固定されること
により、ひとつの半導体装置が構成されている。A single semiconductor device is constructed by being wrapped and fixed from above and below by 16b.
次に、上記構成からなる半導体装置の製造方法の一実施
例を第２図及び第３図に基づいて説明する。Next, an embodiment of a method for manufacturing a semiconductor device having the above structure will be described with reference to FIGS. 2 and 3.
第２図（ａ）〜（ｇｌは、半導体チップとなるシリコン
ウェハーに対するパッドの形成工程を示すものである。FIGS. 2(a) to 2(gl) show the process of forming pads on a silicon wafer that will become a semiconductor chip.
面１通常の半導体形成工程は通常の方法でなされるので
、この工程は同図から省略する。まず、シリコンウェハ
ー６を用意する（第２図（ａ））。Surface 1: Since a normal semiconductor forming process is performed by a normal method, this process is omitted from the figure. First, a silicon wafer 6 is prepared (FIG. 2(a)).
次に第２図（ｂｌに示すように、パッケージとなる部分
に例えばレーザ光を照射して１表裏に貫通する透孔７を
穿つ。次に、第２図（Ｃ）に示すバルク工程では、シリ
コンウェハー６の表面並びに透孔７の周辺に酸化膜（Ｓ
ｉ０２ ）等の絶縁層８を形成する。Next, as shown in FIG. 2 (bl), for example, a laser beam is irradiated on the part that will become the package to make a through hole 7 that penetrates from the front and back.Next, in the bulk process shown in FIG. 2 (C), An oxide film (S
An insulating layer 8 such as i02) is formed.
その後、配線工程で透孔７の周辺に、後述する内側パッ
ド及び外側パッドとなる部分を残して上記の絶縁層８を
除去し、第２図（ｄ）に示すようにアルミニウム（Ａｊ
り等の配線金属９をシリコンウェハー６上の全面に蒸着
する。この配線金属９は。Thereafter, in the wiring process, the insulating layer 8 is removed from the vicinity of the through hole 7, leaving portions that will become inner and outer pads to be described later, and aluminum (Aj) is removed as shown in FIG.
A wiring metal 9 such as wafer is deposited on the entire surface of the silicon wafer 6. This wiring metal 9.
透孔７内に充填される。The through hole 7 is filled.
次に、第２図＋ｅ）に示すように配線金属９をパターニ
ングし、第２図（ｆ）に示すようにシリコンウェハー６
の裏面をｇｆｌｇする。この時、第２図（ｆ）に示す矢
印Ａ方向からみた平面図での外側パッド１０及び内側パ
ッド１１は第２図（ｇｌに示すように形成されている。Next, the wiring metal 9 is patterned as shown in FIG. 2+e), and the silicon wafer 6 is patterned as shown in FIG. 2(f).
gflg the back side of. At this time, the outer pad 10 and the inner pad 11 in a plan view seen from the direction of arrow A shown in FIG. 2(f) are formed as shown in FIG. 2 (gl).
内側パッド１１は、透孔７を介して表面から裏面にかけ
て延び、裏面にパッドｌｌａを形成している。The inner pad 11 extends from the front surface to the back surface through the through hole 7, and forms a pad lla on the back surface.
このような研暦工程が終了したシリコンウェハー６はチ
ップ化される。このような半導体チ・ノブとリードとの
ボンディング工程を第３図（ａｌ〜（ｈｌについて説明
する。The silicon wafer 6 that has been subjected to such a research process is made into chips. The bonding process of such a semiconductor chip knob and a lead will be explained with reference to FIGS.
本実施例では、第３図（ａｌに示すような、仮台１２上
に載置した。第４図に示したリードフレーム２とは異な
るリードフレーム１３を使用する。In this embodiment, the device is placed on a temporary stand 12 as shown in FIG. 3 (al). A lead frame 13 different from the lead frame 2 shown in FIG. 4 is used.
このリードフレーム１３は、略々正方形状の板材に櫛歯
型の２つの打ち抜き部１３ｃ、１３ｃを施すことにより
、その中心部にブリッジ部１３ａを形成すると共に、左
右の両側に複数のり一ド１３ｄを形成したものである。This lead frame 13 is formed by forming two comb-shaped punched parts 13c, 13c in a substantially square plate material, thereby forming a bridge part 13a in the center thereof, and a plurality of glue holes 13d on both left and right sides. was formed.
さらに上記のブリッジ部１３ａには、正方形状のチップ
載置部１３ｂを形成する。このチップ載置部１３ｂ上に
は、第２図に示した工程で形成された半導体チ・７プ１
４を′ａ１固定するが、この際に半導体チップ１４に形
成されているパッドｌｌａ （第２図（ｒ））がチップ
載置部１３ｂのθＩＩＩ部より外側にはみ出る程度の大
きさに選択する。この状態の側断面図を第３図（ｂｌに
示す。すなわち半導体チップ１４のパッドｌｌａの形成
されている両側端を、チップ載置部１３ｂから櫛歯型の
打ち抜き部１３ｃ内にはみ出させ、第２図に示した外側
パッド１０．内側パッド１１．裏面のパッドｌｌａに対
して半導体チップ１４の表裏両面からのボンディングが
可能なように配設する。この状態で、第３図（Ｃ）に示
すように半導体チップ１４の上面のパッド（すなわち、
第２図（ｇ）の外側パッド１０）とリード１３ｄ間をワ
イヤ１５ａでボンディングする。Further, a square chip mounting portion 13b is formed in the bridge portion 13a. On this chip mounting portion 13b, a semiconductor chip 7 formed in the process shown in FIG.
4 is fixed at 'a1', and at this time, the size is selected so that the pad lla (FIG. 2(r)) formed on the semiconductor chip 14 protrudes outside the θIII portion of the chip mounting portion 13b. A side cross-sectional view of this state is shown in FIG. The outer pad 10, the inner pad 11, and the back pad lla shown in FIG. 2 are arranged so that bonding can be performed from both the front and back sides of the semiconductor chip 14. The pads on the top surface of the semiconductor chip 14 (i.e.,
Bonding is performed between the outer pad 10) in FIG. 2(g) and the lead 13d using a wire 15a.
次に、第３図（ｄｌに示すように、ワイヤ１５ａ及び半
導体チップ１４の上面部分を例えば樹脂等で封止するパ
ッケージ１６ａを施す。Next, as shown in FIG. 3 (dl), a package 16a is applied in which the upper surface portions of the wires 15a and the semiconductor chip 14 are sealed with, for example, resin.
次に、第３図（ｅ）に示すように仮台１２を取り除いて
パッケージ１６ａを下側にして、リード１３ｄの裏面を
表出させる。この状態で、チップ載置部１３ｂからはみ
出した半導体チップ１４の裏面の両端が櫛歯型の打ち抜
き部１３ｃに露出しているので、半導体チップ１４の裏
面のパッド（すなわち、第２図（ｆ）のパッド１１ａ）
とり一ド１３ｄ間にワイヤ１５ｂをボンディングする。Next, as shown in FIG. 3(e), the temporary stand 12 is removed, the package 16a is placed on the lower side, and the back surface of the lead 13d is exposed. In this state, both ends of the back surface of the semiconductor chip 14 protruding from the chip mounting portion 13b are exposed to the comb-shaped punched portion 13c. pad 11a)
A wire 15b is bonded between the leads 13d.
ワイヤ１５ａ、１５ｂによるボンディング状態の斜視図
を第３図（ｆ）に示す。FIG. 3(f) shows a perspective view of the bonding state using the wires 15a and 15b.
ボンディング工程が半導体チップ１４の表裏共に終了す
ると、第３図（ｇ）に示すように裏面側のパッケージン
グを行い、樹脂等のパッケージ１６ｂを施す。When the bonding process is completed on both the front and back sides of the semiconductor chip 14, packaging is performed on the back side as shown in FIG. 3(g), and a package 16b made of resin or the like is applied.
上下のバフケージングが完了したら、第３図（ｈｌに示
すようにリード１３ｄのパッケージ１６ａ。After the upper and lower buff caging is completed, the package 16a of the lead 13d is removed as shown in FIG. 3 (hl).
１６ｂから突出した部分を折り曲げ、且つリードフレー
ム１３の共通両側端部１３ｅを切り落とす。The portion protruding from the lead frame 16b is bent, and the common both end portions 13e of the lead frame 13 are cut off.
以上のようにして、第１図に示した半導体装置を完成す
る。In the manner described above, the semiconductor device shown in FIG. 1 is completed.
以上説明したように本発明によれば、半導体チップの表
面のみでなく裏面にもパッドを設けて。As explained above, according to the present invention, pads are provided not only on the front surface of the semiconductor chip but also on the back surface.
両面からワイヤボンディングを可能にしたことにより、
各パッドとパッドの間隔を狭めることなく。By making wire bonding possible from both sides,
without narrowing the distance between each pad.
半導体チン１１個当たりのパッド数を増加させることが
できる。The number of pads per 11 semiconductor chips can be increased.
従って、ＬＳＩ、超ＬＳＩ等の高集積のチップに本発明
を通用した場合でも、ボンディング時におけるワイヤと
ワイヤの交差や接触がな（、容易に信号線を取出すこと
ができる。Therefore, even when the present invention is applied to highly integrated chips such as LSI and VLSI, there is no crossing or contact between wires during bonding (signal lines can be easily taken out).
第１図は本発明に係る半導体装置の一実施例を示す断面
図。
第２図（ａｌ〜（ｇｌは本発明に係る半導体装置の製造
方法の一実施例におけるウェハー上へのパッド形成工程
を示す説明図。
第３図（ａ）〜（ｈ）は同実施例におけるボンディング
工程を示す説明図。
第４図＋ａ）及びｆｂｌは従来の半導体装置のボンディ
ング状態を示す平面図およびそのＡ−Ａ断面図である。
６・・・シリコンウェハー。
７・・・透孔。
８・・・絶縁層。
９・・・配線金属。
１０・・・外側パッド。
１１・・・内側パッド。
１１ａ・ ・・バンド。
１３・・・リードフレーム。
１３ａ・・・ブリッジ部。
１３ｂ・・・チップ載置部。
１３ｄ ・ ・ ・リード。
１４・・・半導体チップ。
１５ａ、１５ｂ・−・・ワイー凱
１６ａ、１６ｂ・・・パッケージ。
パ・ソ々ｒ−一〉
第１図
（０） ？コニニココ２でＥ＝二十〜６ジ）コ
ーウシ＼−第２図
第３図
第４図
■ にＯｌ：FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. FIG. 2 (al to (gl) are explanatory diagrams showing the step of forming pads on a wafer in one embodiment of the method for manufacturing a semiconductor device according to the present invention. An explanatory view showing a bonding process. Fig. 4+a) and fbl are a plan view and a cross-sectional view taken along the line A-A of the bonding state of a conventional semiconductor device. 6... Silicon wafer. 7... Through hole. 8... Insulating layer. 9... Wiring metal. 10... Outer pad. 11... Inner pad. 11a... Band. 13... Lead frame. 13a... Bridge part. 13b... ...Chip placement part. 13d... Lead. 14... Semiconductor chip. 15a, 15b... Y-Kai 16a, 16b... Package. ) ?Koninikoko 2 E = 20~6ji) Koushi ＼ - Figure 2 Figure 3 Figure 4 ■ Ol:
Claims (6)
体装置において、 前記半導体チップの表裏両面に形成されたパッドと、前
記パッケージに固定されたリードとを前記表裏両面から
それぞれワイヤボンディングしたことを特徴とする半導
体装置。(1) A semiconductor device including a semiconductor chip mounted in a package, characterized in that pads formed on both the front and back surfaces of the semiconductor chip and leads fixed to the package are wire-bonded from both the front and back surfaces, respectively. semiconductor device.
導体チップを貫通して形成された導電性接続部を介して
半導体チップの表面に接続されたことを特徴とする特許
請求の範囲第１項記載の半導体装置。(2) The pad formed on the back surface of the semiconductor chip is connected to the front surface of the semiconductor chip through a conductive connection portion formed through the semiconductor chip. The semiconductor device described.
する透孔を形成する工程と、 前記ウェハーの表面に表面パッドを形成し、また前記ウ
ェハーの裏面に前記透孔を介して裏面パッドを形成する
工程と、 前記ウェハーの表裏両面に形成された前記各パッドと、
該パッドと対応するリードとをそれぞれワイヤボンディ
ングする工程と、 該ワイヤボンディングされたウェハーをパッケージする
工程とからなることを特徴とする半導体装置の製造方法
。(3) Forming a through hole penetrating the wafer that will become a semiconductor chip from both sides, forming a front pad on the front surface of the wafer, and forming a back pad on the back surface of the wafer through the through hole. each of the pads formed on both the front and back surfaces of the wafer;
A method for manufacturing a semiconductor device, comprising the steps of wire-bonding the pads and corresponding leads, and packaging the wire-bonded wafer.
酸化して絶縁層を形成し、該絶縁層を含む前記ウェハー
上に配線材料を蒸着して配線をパターニングすることに
より前記パッドを形成することを特徴とする特許請求の
範囲第３項記載の半導体装置の製造方法。(4) After forming the through hole, oxidize a predetermined portion including the through hole to form an insulating layer, and pattern the wiring by depositing a wiring material on the wafer including the insulating layer. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising forming a pad.
ことにより形成されることを特徴とする特許請求の範囲
第３項または第４項記載の半導体装置の製造方法。(5) The method of manufacturing a semiconductor device according to claim 3 or 4, wherein the through hole is formed by irradiating the wafer with laser light.
程と、 上記半導体チップを仮台状に載置したフレーム上に載置
し、少なくとも該チップの端部が該フレーム上のチップ
載置部より突出するように配設して上記フレームとチッ
プの表面パッド間をボンディングする工程と、 半導体チップの表面をパッケージする工程と、上記仮台
を除去して半導体チップの裏面を上面にしてチップの裏
面パッドとリードフレームをボンディングする工程と、 半導体チップの裏面をパッケージする工程とよりなるこ
とを特徴とする特許請求の範囲第３項記載の半導体装置
の製造方法。(6) A step of forming a through hole in a wafer that will become a semiconductor chip; and placing the semiconductor chip on a frame placed in the form of a temporary stand, with at least an end of the chip being placed on a chip mounting portion on the frame. A step of bonding between the frame and the surface pad of the chip by arranging it so that it protrudes more, a step of packaging the front surface of the semiconductor chip, and a step of removing the temporary stand and placing the back side of the semiconductor chip on top. 4. The method of manufacturing a semiconductor device according to claim 3, comprising: a step of bonding a back pad and a lead frame; and a step of packaging a back surface of a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60244411A JPS62104129A (en) | 1985-10-31 | 1985-10-31 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60244411A JPS62104129A (en) | 1985-10-31 | 1985-10-31 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62104129A true JPS62104129A (en) | 1987-05-14 |
Family
ID=17118261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60244411A Pending JPS62104129A (en) | 1985-10-31 | 1985-10-31 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62104129A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009018651A (en) * | 2007-07-11 | 2009-01-29 | East Japan Railway Co | Electric car overhead wire temperature detection device |
-
1985
- 1985-10-31 JP JP60244411A patent/JPS62104129A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009018651A (en) * | 2007-07-11 | 2009-01-29 | East Japan Railway Co | Electric car overhead wire temperature detection device |
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