JPH04167534A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04167534A JPH04167534A JP2294613A JP29461390A JPH04167534A JP H04167534 A JPH04167534 A JP H04167534A JP 2294613 A JP2294613 A JP 2294613A JP 29461390 A JP29461390 A JP 29461390A JP H04167534 A JPH04167534 A JP H04167534A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- leads
- chip
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 abstract description 7
- 239000007767 bonding agent Substances 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置、特にスーテージレスのパッケージの半導体
装置と製造方法に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device, particularly a semiconductor device and manufacturing method of a stageless package.
リードフレームのリード配列を簡易にし、またリードフ
レームの各種チップに対する汎用性を増やすことを目的
とし。The purpose is to simplify the lead arrangement of lead frames and increase the versatility of lead frames for various types of chips.
■）半導体チップと、該チップ表面上の配線用パッド以
外の領域に接着された絶縁フィルムと、該絶縁フィルム
の上に形成された導電膜からなる中間配線と、外部接続
用のリードとを有し、該バットと該リードが該中間配線
を介して接続されているように構成する。(2) It has a semiconductor chip, an insulating film bonded to an area other than the wiring pad on the surface of the chip, intermediate wiring made of a conductive film formed on the insulating film, and leads for external connection. The butt and the lead are connected via the intermediate wiring.
２）パッド部以外の半導体チップの表面に中間配線が形
成された絶縁フィルムを接着する工程と。2) A step of adhering an insulating film on which intermediate wiring is formed to the surface of the semiconductor chip other than the pad portion.
該パッドと該中間配線とをボンディングする工程と、該
中間配線とリードフレームのリード間を接続する工程と
を有するように構成する。The method is configured to include a step of bonding the pad and the intermediate wiring, and a step of connecting the intermediate wiring and the leads of the lead frame.
本発明は半導体装置、特にステージレスのパッケージの
半導体装置と製造方法に関する。The present invention relates to a semiconductor device, and particularly to a stageless package semiconductor device and manufacturing method.
第４図は従来の樹脂封止の半導体装置の平面図である。 FIG. 4 is a plan view of a conventional resin-sealed semiconductor device.
従来の樹脂封止の半導体装置においては、チップ２の周
辺部に形成された配線用パッドｌはリードフレームのリ
ード３とワイヤボンディングによって接続されていた。In a conventional resin-sealed semiconductor device, wiring pads 1 formed around the periphery of the chip 2 are connected to leads 3 of a lead frame by wire bonding.
ところが、近年の半導体装置の高集積化にともない半導
体チップは大型化される傾向にあるが。However, as semiconductor devices have become more highly integrated in recent years, semiconductor chips have tended to become larger.
これに対し半導体装置の形状は互換性や実装の高密度化
の要求により自由に大型化することはできない。On the other hand, the shape of a semiconductor device cannot be freely increased in size due to demands for compatibility and higher packaging density.
このため、最近ではチップを載せるステージのないステ
ージレスのパッケージが用いられるようになった（例え
ば、特開昭６１−２１８１３９．特開昭６２−１５４７
６４等参照）。For this reason, stageless packages that do not have a stage on which chips are placed have recently come into use (for example, Japanese Patent Application Laid-Open Nos. 61-218139, 1982-1547).
64 etc.).
従来技術によれば、リードフレームのリードのレイアウ
トが複雑であり、 ＩＣの品種に対して汎用性が少なく
、またチップサイズごとにリードフレームを準備する必
要があった。According to the conventional technology, the lead frame lead layout is complicated, there is little versatility with respect to IC types, and it is necessary to prepare lead frames for each chip size.
本発明はリードフレームのリード配列を簡易にし、また
リードフレームの各種チップに対する汎用性を増やすこ
とを目的とする。An object of the present invention is to simplify the lead arrangement of a lead frame and to increase the versatility of the lead frame for various types of chips.
上記課題の解決は。 What is the solution to the above problem?
１）半導体チップと、該チップ表面上の配線用パッド以
外の領域に接着された絶縁フィルムと、該絶縁フィルム
の上に形成された導電膜からなる中間配線と、外部接続
用のリードとを有し、該パッドと該リードが該中間配線
を介して接続されている半導体装置あるいは。1) It has a semiconductor chip, an insulating film adhered to an area other than the wiring pads on the surface of the chip, intermediate wiring made of a conductive film formed on the insulating film, and leads for external connection. and a semiconductor device in which the pad and the lead are connected via the intermediate wiring.
２）パッド部以外の半導体チップの表面に中間配線が形
成された絶縁フィルムを接着する工程と。2) A step of adhering an insulating film on which intermediate wiring is formed to the surface of the semiconductor chip other than the pad portion.
該パッドと該中間配線とをボンディングする工程と、該
中間配線とリードフレームのリード間を接続する工程と
を有する前記１）記載の半導体装置の製造方法により達
成される。This is achieved by the method for manufacturing a semiconductor device described in 1) above, which includes the steps of bonding the pad and the intermediate wiring, and connecting the intermediate wiring and the leads of the lead frame.
本発明はパッド部以外の半導体チップ上に絶縁フィルム
を接着し、その上に導電膜からなる中間配線を接着し、
チップとリードフレームのリード間を中間配線を介して
接続するようにし、この中間隙配線のリードフレーム側
接続端のレイアウトを一定にすることにより、この中間
配線に対応するリードフレームのリードのレイアウトを
チップの種類にかかわらず簡易化するようにしたもので
ある。In the present invention, an insulating film is bonded on the semiconductor chip other than the pad portion, and an intermediate wiring made of a conductive film is bonded on top of the insulating film.
By connecting the leads of the chip and the lead frame via an intermediate wiring, and by making the layout of the connection end of this intermediate wiring on the lead frame side constant, the layout of the leads of the lead frame corresponding to this intermediate wiring can be changed. It is designed to be simplified regardless of the type of chip.
第１図は本発明の一実施例による半導体装置の平面図で
ある。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
図において、１はチップ上に形成されたパッド。In the figure, 1 is a pad formed on the chip.
２は半導体チップ、３はビームリードのリード。2 is a semiconductor chip, and 3 is a beam lead.
４は封止樹脂、５は絶縁フィルム、６は中間配線。4 is a sealing resin, 5 is an insulating film, and 6 is an intermediate wiring.
７はワイヤである。7 is a wire.
この例では、チップ２の周辺部に形成された配線用パッ
ト１を除いて、チップ２の→俵面は絶縁フィルム５て被
覆され接着されている。In this example, except for the wiring pads 1 formed around the periphery of the chip 2, the surface of the chip 2 is covered with an insulating film 5 and bonded.
絶縁フィルム５の上には導電膜からなる中間配線６が接
着されている。An intermediate wiring 6 made of a conductive film is adhered onto the insulating film 5.
バンドｌと中間配線６の一端はワイヤボンディングされ
る。The band 1 and one end of the intermediate wiring 6 are wire bonded.
リードフレームのり一部３の先端以外は絶縁されており
、リート３の先端と中間配線６とが導電性接着剤で接続
されるわ
ここで、リードフレームと中間配線の接続を先に行い、
その後にチップと中間配線をワイヤボンディングしても
よいが、実施例の順序のようにワイヤホンディング後に
リードフレームの接続を行う方が、ワイヤボンディング
時の加熱によりリードフレームが酸化され、樹脂封止の
気密性が低下するという悪影響を抑制できる。The parts other than the tip of the lead frame glue part 3 are insulated, and the tip of the lead frame 3 and the intermediate wiring 6 are connected with conductive adhesive. At this point, first connect the lead frame and the intermediate wiring.
The chip and intermediate wiring may be wire-bonded after that, but it is better to connect the lead frame after wire bonding as in the order of the example, since the lead frame will be oxidized by the heat during wire bonding, and the resin sealing The negative effect of a decrease in airtightness can be suppressed.
ここで、絶縁フィルム５は厚さ２５μｍのポリイミド膜
を使用し、チップ表面にエポキシ系の接着剤を用いて接
着した。Here, the insulating film 5 was a polyimide film with a thickness of 25 μm, and was adhered to the chip surface using an epoxy adhesive.
また、中間配線６は導電膜として厚さ２０〜３５μｍの
銅膜を絶縁フィルム５上にエポキシ系の接着剤を用いて
接着し９通常のりソグラフィを用いてパターニングして
形成した。Further, the intermediate wiring 6 was formed by adhering a copper film having a thickness of 20 to 35 μm as a conductive film onto the insulating film 5 using an epoxy adhesive, and patterning the film using normal glue lithography.
また、リードフレーム接続用の導電性接着剤は銀（Ａｇ
）入りのエポキシ系の接着剤を用いた。In addition, the conductive adhesive for lead frame connection is silver (Ag
) was used.
また、リードフレームのリードの先端部以外の絶縁は以
下のように行った。Further, insulation of the parts other than the tips of the leads of the lead frame was performed as follows.
先端部をマスキングし、絶縁用のエポキシ系の樹脂を裏
面のみに塗布するか、もしくは絶縁テープでテーピング
する。Mask the tip and apply insulating epoxy resin only to the back side, or tape it with insulating tape.
第２図は他の実施例による半導体装置の平面図である。FIG. 2 is a plan view of a semiconductor device according to another embodiment.
第１図の実施例では、リードフレームのリードは先端部
以外は絶縁されているが、この例はパッドＩをチップ２
の中央部に配置し、中間配線６を必要箇所のみに配置し
てリードと中間配線が交差しないようにしているため、
リードは絶縁しなくてもよいように構成されている。In the embodiment shown in FIG. 1, the leads of the lead frame are insulated except for the tips, but in this example, the pad I is connected to the chip 2.
The intermediate wiring 6 is placed only in necessary locations to prevent the leads and intermediate wiring from intersecting.
The leads are constructed so that they do not need to be insulated.
第３図はチップが非常に小さいときの実施例の平面図で
ある。FIG. 3 is a plan view of an embodiment in which the chip is very small.
この図では、第１図の実施例より、チップが小さくなり
右側にシフトして配置されているときの配線が示されて
いる。This figure shows the wiring when the chip is smaller and shifted to the right side compared to the embodiment of FIG. 1.
実施例ではワイヤボンディングを用いたが。Although wire bonding was used in the embodiment.
ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎ
ｇ）用のフィルムを用いる方法もある。TAB (Tape Automated Bondin)
There is also a method using a film for (g).
ＴＡＢフィルムを用いるときは、バンプ（ＴＡＢフィル
ム側に形成された）を用いてチップに直接ボンディング
している。When a TAB film is used, bumps (formed on the TAB film side) are used to bond directly to the chip.
しかしながら、汎用性を考えるとＴＡＢフィルム法では
中間配線のパターンを品種ごとに作らなければならず、
製造原価高となる。However, when considering versatility, the TAB film method requires that intermediate wiring patterns be created for each product type.
Manufacturing costs will be high.
これに対し、ワイヤボンディング法の場合は少々の斜め
配線も可能で汎用性があり、またバンプも不要である。On the other hand, the wire bonding method allows for slightly diagonal wiring, is versatile, and does not require bumps.
以上説明したように本発明によれば、リードフレームの
リード配列を簡易にし、またリードフレームの各種チッ
プに対する汎用性を増やすことが可能となった。As described above, according to the present invention, it is possible to simplify the lead arrangement of a lead frame and increase the versatility of the lead frame for various types of chips.
この結果、リードフレームのプレス型が簡略化され大幅
なコストダウンどなり、また、ワイヤボンディングがチ
ップ状態で行え、ワイヤボンディング時の熱によるリー
ドフレームの酸化が防止され半導体装置の耐湿性が向上
した。As a result, the press die for the lead frame was simplified, resulting in a significant cost reduction. Also, wire bonding could be performed in the chip state, preventing oxidation of the lead frame due to heat during wire bonding, and improving the moisture resistance of semiconductor devices.
第１図は本発明の一実施例による半導体装置の平面図。 第２図は他の実施例による半導体装置の平面図。 第３図はチップが非常に小さいときの実施例の平面図。 第４図は従来の樹脂封止の半導体装置の平面図である。 図において。 １はチップ上のパッド。 ２は半導体チップ。 ３はリード。 ４は封止樹脂。 ５は絶縁フィルム。 ６は中間配線。 ７はワイヤ 実方巳イ列の平面図 第１図 他ｆ）実方色佼ｊの平面図 第 ２ 図 小÷・ノブの実１ｒ＝４列の十面図 第 ３ 図 イ足米分・ｊの平面図 譚 ４ 図 FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of a semiconductor device according to another embodiment. FIG. 3 is a plan view of an embodiment in which the chip is very small. FIG. 4 is a plan view of a conventional resin-sealed semiconductor device. In fig. 1 is a pad on the chip. 2 is a semiconductor chip. 3 is the lead. 4 is sealing resin. 5 is an insulating film. 6 is intermediate wiring. 7 is wire Plan of the Jitsuhomi series Figure 1 Other f) Plan view of Jitsuho Shikiji Figure 2 Small ÷ Knob fruit 1r = 4 rows of ten-sided diagram Figure 3 Floor plan of Ishimibun・j Tan 4 figure
Claims (1)
外の領域に接着された絶縁フィルムと、該絶縁フィルム
の上に形成された導電膜からなる中間配線と、外部接続
用のリードとを有し、 該パッドと該リードが該中間配線を介して接続されてい
ることを特徴とする半導体装置。２）パッド部以外の半
導体チップの表面に中間配線が形成された絶縁フィルム
を接着する工程と、該パッドと該中間配線とをボンディ
ングする工程と、 該中間配線とリードフレームのリード間を接続する工程
とを有することを特徴とする請求項１記載の半導体装置
の製造方法。[Scope of Claims] 1) A semiconductor chip, an insulating film bonded to an area other than the wiring pad on the surface of the chip, an intermediate wiring made of a conductive film formed on the insulating film, and an external connection. What is claimed is: 1. A semiconductor device comprising: a lead for use in the semiconductor device, the pad and the lead being connected via the intermediate wiring. 2) A step of adhering an insulating film on which an intermediate wiring is formed on the surface of the semiconductor chip other than the pad portion, a step of bonding the pad and the intermediate wiring, and a step of connecting the intermediate wiring and the leads of the lead frame. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2294613A JPH04167534A (en) | 1990-10-31 | 1990-10-31 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2294613A JPH04167534A (en) | 1990-10-31 | 1990-10-31 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04167534A true JPH04167534A (en) | 1992-06-15 |
Family
ID=17810028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2294613A Pending JPH04167534A (en) | 1990-10-31 | 1990-10-31 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04167534A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883427A (en) * | 1996-09-10 | 1999-03-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device power supply wiring structure |
-
1990
- 1990-10-31 JP JP2294613A patent/JPH04167534A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883427A (en) * | 1996-09-10 | 1999-03-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device power supply wiring structure |
| US6181005B1 (en) | 1996-09-10 | 2001-01-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device wiring structure |
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