JP2002158309A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein work of a substrate which uses tape base substance is standardized, failure due to bending of a lead is reduced, and a product of a narrow pad pitch can be realized. SOLUTION: A semiconductor device of a T-TFBGA package using a COF structure consists of a substrate 1 wherein a wiring layer is formed on the tape base substance 5, a chip 2 mounted on a surface of the substrate 1, sealing agent 3 for sealing a connection part between the chip 2 and the substrate 1, external terminals 4 mounted on the back of the substrate 1, etc. In a package structure, a wiring pattern 6 on the tape base substance 5 of the substrate 1 and the chip 2 mounted on the substrate 1, and the external terminals 4 of the package are positioned on the opposite sides interposing the tape base substance 5 of the substrate 1. As a result, device holes of the tape base substance 5 are unnecessary, and a lead part 7 of the substrate 1 which is connected with an electrode 11 of the chip 2 by using a wiring is fixed on the tape base substance 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, for example, a COF (ChipOn).
T-TFBGA (Tape-T) using a (Film) structure
Hin Finepitch Ball Grid A
The present invention relates to a semiconductor device suitable for a package and the like and a technique effective when applied to a method for manufacturing the same.

[0002]

2. Description of the Related Art As a technique studied by the present inventors, for example, a T-TFBGA package is a TAB (Tape A).
The package structure is such that a chip is mounted using an automated bonding method and solder balls, which are external terminals of the package, are provided outside the mounted chip. In this TAB method, the polyimide tape as a main member has (1) a device hole for mounting a chip, and (2) a wiring between the chip and external terminals is formed by etching a copper foil provided on the tape. A land for mounting the wiring pattern and the solder ball is formed.

[0003] As a technology relating to such a TAB package, for example, July 28, 2000
Published by Japan Industrial Research Institute, Inc., Japan Electronics Packaging Association, edited by "Electronics Packaging Encyclopedia" P59
1 to P594.

[0004]

The inventors of the present invention have studied the technology of the TAB type package as described above, and as a result, the following has become clear.

(1) T-TFBGA using TAB structure
In the package, it is necessary to provide a device hole for mounting a product for each product chip size on a polyimide tape, which is a main member, and it is necessary to manufacture a die for punching this tape for each product.

(2) When the pad pitch of the product chip is narrow, the T-TFBGA package using the TAB structure easily causes a defect due to lead bending since the inner lead protrudes into the device hole.

(3) T-TFBGA using TAB structure
Since the package can arrange the external terminals of the package only outside the mounted chip, the maximum number of the external terminals is limited.

Therefore, an object of the present invention is to provide, for example, COF
Apply to T-TFBGA package using structure
An object of the present invention is to provide a semiconductor device capable of standardizing the processing of a substrate using a tape base material, reducing defects due to lead bending, and realizing a product with a narrow pad pitch, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor device according to the present invention, a wiring layer is formed on the surface of a tape base material, and a lead portion and a land portion are provided at both ends of a wiring pattern of the wiring layer. A substrate having an opening formed in the tape base so as to be exposed, and an electrode portion mounted face-down on the surface of the substrate and connected to a predetermined integrated circuit on the surface; Is connected to the lead portion, a sealing material for sealing a connection portion between the electrode portion of the chip and the lead portion of the substrate, and mounted on the back surface of the substrate and connected to the land portion through the opening. And an external terminal.

In the semiconductor device, the external terminals are mounted on the back surface of the substrate, outside the chip mounting area, or outside and inside. A plurality of chips are mounted on the surface of the substrate.

In the method of manufacturing a semiconductor device according to the present invention, a wiring layer is formed on a surface of a tape base material, and a lead portion and a land portion are provided at both ends of a wiring pattern of the wiring layer. One or a plurality of chips provided with an electrode portion connected to a predetermined integrated circuit on the surface are formed on a surface of a substrate in which an opening is formed in a tape base so as to be exposed on the back surface side. The chip electrode is mounted face-down so that it is connected to the lead, the connection between the electrode of one or more chips and the lead of the substrate is sealed with a sealing material, And mounting an external terminal so as to be connected to the land through the opening.

Therefore, according to the semiconductor device and the method of manufacturing the same, the wiring layer on the tape base of the substrate, the chip mounted on the substrate, and the external terminals of the package are on opposite sides of the tape base of the substrate. , The device hole of the tape substrate is not required, and the standardization of the substrate processing can be achieved. Further, since the lead portion of the substrate connected to the electrode portion of the chip is fixed on the tape base, it is possible to reduce defects due to lead bending. Further, since the external terminals of the package are located on the opposite side of the chip with the tape base material interposed therebetween, the external terminals can be mounted on the inner region of the mounted chip.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) First, the configuration of an example of the semiconductor device of the present embodiment will be described with reference to FIGS. 1 is a plan view showing a semiconductor device of the present embodiment, FIG. 2 is a bottom view showing the semiconductor device, FIG. 3 is a cross-sectional view showing the semiconductor device, and FIG. 4 is an enlarged view showing a main part (X part) of FIG. It is sectional drawing.

The semiconductor device according to the present embodiment has a C
Substrate 1 having a T-TFBGA package semiconductor device using an OF structure and having a wiring layer formed on a tape base material
A chip 2 mounted on the surface of the substrate 1, a sealing material 3 for sealing a connection portion between the chip 2 and the substrate 1,
It comprises external terminals 4 mounted on the back surface of the substrate 1 and the like.

In the substrate 1, a wiring layer is formed on the surface of a tape base material 5, and a lead portion 7 and a land portion 8 are provided at both ends of each wiring pattern 6 of the wiring layer. An opening 9 is formed in the tape base 5 so as to be exposed to the outside. The wiring pattern 6 on the surface of the substrate 1 is covered with a solder resist 10 except for the lead portions 7. In the substrate 1, for example, the tape base 5 is made of a polyimide resin, and the wiring pattern 6 is made of a copper (Cu) foil.

The chip 2 has, for example, an ASI
An electrode unit 11 connected to a predetermined integrated circuit such as a microcomputer, a microcomputer, and a memory is provided. This chip 2 is mounted face down on the surface of the substrate 1,
The electrode section 11 is electrically connected to the lead section 7 of the substrate 1. The chip 2 has, for example, a gold (Au) electrode portion 11.
It consists of bumps and the like.

The sealing material 3 is made of, for example, a polyimide resin for sealing a connection portion between the electrode portion 11 of the chip 2 and the lead portion 7 of the substrate 1.

The external terminal 4 is mounted on the back surface of the substrate 1 and is electrically connected to the land 8 through the opening 9 of the tape base 5 of the substrate 1, for example, tin (Sn) /
It is made of a solder ball of lead (Pb) or lead-free.

In the semiconductor device of the T-TFBGA package configured as described above, the external terminals 4 are arranged in two rows outside the mounting area of the chip 2. Further, in order to prevent deformation of the substrate 1 made of the tape base material 5, a reinforcing frame 12 is attached on the surface of the substrate 1.

Next, referring to FIGS. 5 and 6, an example of a tape member used as a material of the substrate will be described. FIG. 5 is a plan view showing the tape member of the substrate, and FIG. 6 is a cross-sectional view (a-a ′ cutting line in FIG. 5) showing the tape member of the substrate.

The tape member is connected in series and wound in a reel shape, for example, in order to accommodate a plurality of packages, or is formed in a strip shape in a plurality of units. 5 and 6 show a portion of the substrate 1 corresponding to one package.

The main member of this tape member is a tape base material 5 made of, for example, a polyimide resin, and a plurality of wiring patterns 6 made of, for example, copper (Cu) foil are formed on the surface thereof. At both ends of each wiring pattern 6, a lead portion 7 connected to the electrode portion 11 of the chip 2 is provided.
And a land 8 connected to the external terminal 4 through the opening 9 of the tape base 5. Further, each wiring pattern 6 is covered with a solder resist 10 except for the lead portion 7. Further, on both sides of the tape member, sprocket holes 13 to be inserted at the time of conveyance are provided. The tape member has no device hole.

Next, an example in which the semiconductor device of the T-TFBGA package is mounted on a mounting board will be described with reference to FIG. FIG. 7 is a side view showing a state where the semiconductor device is mounted on a mounting board.

The semiconductor device of the T-TFBGA package is mounted on, for example, a mounting board 14 having a multilayer wiring layer structure together with other semiconductor devices and electronic components, and is housed in a device such as a computer for use.

Next, a method of manufacturing a semiconductor device of a T-TFBGA package according to the present embodiment will be described with reference to FIGS. 8 and 9, the left-side diagrams are flow charts showing respective manufacturing steps of the manufacturing method, and the right-side figures are cross-sectional views showing semiconductor devices corresponding to the respective manufacturing steps.

Prior to the manufacture of the semiconductor device, as a preparatory step, a tape member, a chip 2, a sealing material 3, and an external material, which are necessary for the manufacture of a T-TFBGA package semiconductor device and serve as a material of the substrate 1, are provided. A solder ball serving as the terminal 4 and a reinforcing frame 12 are prepared.

(1) In the chip mounting step (step S1), each chip 2 is placed on the surface of the substrate 1 corresponding to one package of the tape member, and the electrode portion 1 of the chip 2
1 is mounted face down so as to be connected to the lead portion 7 of the substrate 1.

(2) In the sealing step (step S2), the connection between the electrode portion 11 of each chip 2 and the lead portion 7 of the substrate 1 is sealed with the sealing material 3.

(3) In the frame attaching step (step S3), the reinforcing frame 12 is attached on the surface of the substrate 1. This frame attaching step can be performed before the chip mounting step.

(4) In the ball mounting step (step S4), the tape base material 5 of the substrate 1
A solder ball to be the external terminal 4 is mounted so as to be connected to the land portion 8 through the opening 9 of FIG.

(5) In the tape cutting step (step S5), the chip 2 is mounted, sealed with the sealing material 3, the reinforcing frame 12 is attached, and the tape member substrate 1 on which the external terminals 4 are mounted. Is cut for each package.

Thus, the semiconductor device of the T-TFBGA package is completed. In this semiconductor device, each terminal of the integrated circuit inside the chip 2 is electrically connected to the external terminal 4 of the solder ball through the electrode portion 11 and further through the lead portion 7, the wiring pattern 6, and the land portion 8 of the substrate 1. You.

Therefore, according to the semiconductor device of the present embodiment, the wiring pattern 6 on the tape base material 5 of the substrate 1, the chip 2 mounted on the substrate 1, and the external terminals 4 of the package are formed on the tape of the substrate 1. Since the package structure is located on the opposite side with respect to the base member 5, no device hole of the tape base member 5 is required, so that the processing of the substrate 1 can be standardized. Further, since the lead portions 7 of the substrate 1 connected to the electrode portions 11 of the chip 2 are fixed on the tape base 5, defects due to lead bending can be reduced.

(Embodiment 2) First, the configuration of an example of the semiconductor device of the present embodiment will be described with reference to FIGS. FIG. 10 is a plan view showing a semiconductor device of this embodiment,
11 is a bottom view showing the semiconductor device, FIG. 12 is a sectional view showing the semiconductor device, and FIG. 13 is an enlarged sectional view showing a main part (Y part) of FIG.

As in the first embodiment, the semiconductor device according to the present embodiment is, for example, a T-TF having a COF structure.
The semiconductor device is a BGA package semiconductor device, and differs from the first embodiment in that external terminals are mounted on the back surface of the substrate outside and inside the chip mounting region.

That is, the semiconductor device of this embodiment is
A substrate 1a having a wiring layer formed on a tape substrate, a chip 2 mounted on the surface of the substrate 1a,
Encapsulating material 3 for sealing a connection portion between the substrate 1a and the substrate 1a;
a of the chip 2 as in the first embodiment.
Are arranged in two rows outside the mounting area of
a are arranged in one line inside the mounting area of the chip 2.

Next, an example of a tape member used as a material of the substrate will be described with reference to FIGS. FIG. 14 is a plan view showing the tape member of the substrate, and FIG. 15 is a cross-sectional view (section line bb 'in FIG. 14) showing the tape member of the substrate.

As in the first embodiment, the main member of the tape member is made of a tape base material 5a made of, for example, a polyimide resin, and copper (Cu) is formed on the surface thereof.
A plurality of wiring patterns 6, 6a made of foil or the like are formed. At both ends of each of the wiring patterns 6 and 6a, lead terminals 7 and 7a connected to the electrode unit 11 of the chip 2 and external terminals 4 and 4 through openings 9 and 9a of the tape base 5a.
Land portions 8 and 8a connected to a are provided.

Particularly, in the present embodiment, each wiring pattern 6 and the lead portions 7 and the land portions 8 provided at both ends thereof are arranged outside the mounting area of the chip 2 as in the first embodiment. ing. New wiring patterns 6a
In addition, lead portions 7a and land portions 8a provided at both ends are added, and these wiring patterns 6a, lead portions 7a and land portions 8a are arranged inside the mounting area of the chip 2.

The structure and the manufacturing method of the other elements constituting the semiconductor device of the T-TFBGA package are the same as those in the first embodiment, so that the detailed description is omitted here.

Therefore, according to the semiconductor device of the present embodiment, the wiring patterns 6 and 6a on the tape base 5a of the substrate 1a and the chip 2 mounted on the substrate 1a are similar to the first embodiment. And the external terminals 4 and 4a of the package have a package structure located on the opposite side of the substrate 1a with the tape base 5a interposed therebetween, and do not require device holes in the tape base 5a. I can do it. Further, a substrate 1a connected to the electrode portion 11 of the chip 2
Since the lead portions 7, 7a are fixed on the tape base material 5a, defects due to lead bending can be reduced.

Further, in this embodiment, the external terminals 4 and 4a of the package are connected to the chip 2 with the tape base 5a interposed therebetween.
The external terminals 4a can also be mounted in the area inside the chip 2 to be mounted.

When the external terminal 4a is mounted inside the mounting area of the chip 2 as in this embodiment, for example, as shown by a broken line in FIG. 14, the external terminal 4a is connected to a power supply (VDD), By applying to a terminal such as ground (VSS), it is also possible to connect two or more lands 8a with a wiring pattern.

(Embodiment 3) The configuration of an example of the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 16 is a sectional view showing the semiconductor device of the present embodiment.

The semiconductor device of the present embodiment is, for example, a semiconductor device of a T-TFBGA package using a COF structure, similar to the first and second embodiments, and is different from the first and second embodiments. Is that a plurality of chips are mounted on the surface of the substrate.

That is, the semiconductor device of this embodiment is
A substrate 1b having a wiring layer formed on a tape base material and, for example, two chips 2 mounted on the surface of the substrate 1b
a, 2b, a sealing material 3 for sealing a connection portion between the chips 2a, 2b and the substrate 1b, an external terminal 4 mounted on the back surface of the substrate 1b, and the like.
A predetermined integrated circuit such as a memory is formed on the chip 2b.

The structure and the manufacturing method of the other elements constituting the semiconductor device of the T-TFBGA package are the same as those in the first embodiment, and the detailed description is omitted here.

Therefore, according to the semiconductor device of the present embodiment, similarly to the first and second embodiments, the wiring pattern 6b on the tape base 5b of the substrate 1b and the wiring pattern 6b of the substrate 1b
Since the chips 2a and 2b mounted thereon and the external terminals 4 of the package have a package structure located on the opposite side of the substrate 1b with the tape base 5b interposed therebetween, the device holes of the tape base 5b are not required. Standardization of the processing of the substrate 1b can be achieved. Further, since the leads of the substrate 1b connected to the electrodes of the chips 2a and 2b are fixed on the tape base 5b, defects due to lead bending can be reduced.

In this embodiment, as in the second embodiment, the external terminals 4 of the package are located on the opposite side of the chips 2a and 2b with the tape base 5b interposed therebetween. External terminals can also be mounted on the inner regions of the chips 2a and 2b.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, C
The semiconductor device of the T-TFBGA package using the OF structure has been described as an example, but is not limited thereto.
It can be widely applied to all packages with COF structure using a substrate made of a tape substrate, and the wiring pattern on the tape substrate of the substrate and the external terminals of the chip and package mounted on this substrate are the tape substrate of the substrate What is necessary is just a package structure located on the opposite side with respect to.

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The wiring pattern on the tape base material of the substrate and the chip mounted on the substrate and the external terminals of the semiconductor device have a structure located on the opposite side of the substrate with the tape base material interposed therebetween. Since no device hole is required, standardization of substrate processing can be achieved.

(2) Since the lead of the substrate connected to the electrode of the chip is fixed on the tape base material, it is possible to reduce defects due to lead bending.

(3) Since the external terminals of the semiconductor device are located on the opposite side of the chip with the tape base material interposed therebetween, it is possible to mount the external terminals also in a region inside the mounted chip.

(4) According to the above (1), standardization of tape processing can be achieved, so that tape processing costs can be reduced.

(5) According to the above (2), defects due to lead bending can be reduced, so that the tape yield and the assembly yield can be improved.

(6) According to the above (2), defects due to lead bending can be reduced, so that a product with a narrow pad pitch can be produced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a bottom view illustrating the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view showing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 4 is an enlarged sectional view showing a main part (X part) of FIG. 3.

FIG. 5 shows a semiconductor device according to the first embodiment of the present invention.
It is a top view showing the tape member of a substrate.

FIG. 6 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 6 is a cross-sectional view showing the tape member of the substrate cut along the cutting line aa ′ in FIG. 5.

FIG. 7 is a side view showing a state where the semiconductor device according to the first embodiment of the present invention is mounted on a mounting board.

FIG. 8 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention (following FIG. 8).

FIG. 10 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a bottom view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 13 is an enlarged cross-sectional view illustrating a main part (Y part) of FIG. 12 in the semiconductor device according to the second embodiment of the present invention;

FIG. 14 is a plan view showing a tape member of a substrate in the semiconductor device according to the second embodiment of the present invention;

FIG. 15 is a cross-sectional view showing the tape member of the substrate, cut along the line bb ′ in FIG. 14, in the semiconductor device according to the second embodiment of the present invention;

FIG. 16 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

 1, 1a, 1b substrate 2, 2a, 2b chip 3 sealing material 4, 4a external terminal 5, 5a, 5b tape base material 6, 6a, 6b wiring pattern 7, 7a lead portion 8, 8a land portion 9, 9a opening Part 10 Solder resist 11 Electrode part 12 Reinforcement frame 13 Sprocket hole 14 Mounting board

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Seiichi Ichihara 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5F044 KK03 LL00 MM03 MM08 MM16 MM48 RR18

Claims (5)

[Claims] 1. A wiring layer is formed on a surface of a tape base material, and a lead portion and a land portion are provided at both ends of a wiring pattern of the wiring layer, and the tape base is exposed such that the land portion is exposed on the back surface side. A substrate having an opening formed in the material; and an electrode portion mounted face-down on the surface of the substrate and connected to a predetermined integrated circuit on the surface, and the electrode portion is connected to the lead portion. A chip to be sealed, a sealing material for sealing a connection portion between an electrode portion of the chip and a lead portion of the substrate, and an external device mounted on a back surface of the substrate and connected to the land portion through the opening. A semiconductor device having a terminal. 2. The semiconductor device according to claim 1, wherein the external terminal is mounted on a rear surface of the substrate and outside a mounting region of the chip. 3. The semiconductor device according to claim 1, wherein said external terminals are mounted on a back surface of said substrate, outside and inside a mounting region of said chip. 4. The semiconductor device according to claim 1, wherein a plurality of chips are mounted on a surface of said substrate. 5. A wiring layer is formed on a surface of a tape base material, and a lead portion and a land portion are provided at both ends of a wiring pattern of the wiring layer, and the tape base is exposed such that the land portion is exposed on the back surface side. One or a plurality of chips provided with an electrode portion connected to a predetermined integrated circuit on the surface of a substrate having an opening formed in a material, and the electrode portion of the chip is connected to the lead portion. A step of mounting face-down so as to be connected; a step of sealing a connection portion between the electrode portion of the one or more chips and the lead portion of the substrate with a sealing material; Mounting an external terminal so as to be connected to the land through the opening.