JPS6198381A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a display control device, and for example, to a technology that is effective when used in a display control device that draws characters or figures on a liquid crystal display panel with a dot matrix configuration. It is.

[Background technology]

Conventionally, liquid crystal display devices with a dot matrix configuration have been
For example, “Electronic Materials 1 Magazine, October 1980 issue, page 1, 21
- page 43. In a display device using a conventional liquid crystal display panel having a dot matrix structure, display data is formed by a microprocessor, stored in a refresh memory, and repeatedly read out according to display timing for display. This refresh memory is composed of RAM (Random Access Memory). In such display control, when displaying alphabento characters and numbers, the encoded information is converted into display data corresponding to the dot matrix. On the other hand, when drawing an arbitrary figure, it is necessary to write bit information corresponding to the dots of the figure into the refresh memory. Therefore, when displaying a composite of characters, etc. and graphics, the display methods are different, making it extremely difficult to control.

[Purpose of the invention]

An object of the present invention is to provide a display control device that can combine and display characters and graphics with a simple configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

A brief summary of typical inventions disclosed in this application is as follows.

That is, the memory area of the refresh memory is divided, addresses are generated that alternately designate the character information area and the graphic information area during the unit display timing period, and the read signals are synthesized. .

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention.

In the figure, the liquid crystal display panel LCD has scanning electrodes running in the horizontal direction and signal electrodes running in the vertical direction, and display dots are formed at the intersections of the two, and a predetermined display is performed depending on the brightness and darkness of the dots. be exposed. Since such a dot matrix liquid crystal display panel LCD is well known, a detailed explanation of its structure and operating principle will be omitted.

A selection drive signal is sequentially supplied to the scan electrodes of the liquid crystal display panel LCD by a scan electrode drive circuit R-DRV. This scanning electrode drive circuit R-D'RV is
Although not particularly limited, it is constituted by a one-chip seven-nolithic semiconductor integrated circuit device, and forms a multi-value pulse drive signal for AC driving a liquid crystal. For example, such a scanning electrode drive circuit R-DRV can be made using a semiconductor integrated circuit device such as HD44100HJ sold by Hitachi.

The signal electrodes of the liquid crystal display panel LCD are supplied with display signals formed by a signal electrode drive circuit C-DRV configured by a one-chip monolithic semiconductor integrated circuit device, although not particularly limited thereto. Signal electrode drive circuit C-
DRV forms a multi-value pulse drive signal similar to the above. This signal electrode drive circuit C-DRV includes a shift register that receives serially supplied display data, converts it into a parallel signal, and forms a display signal corresponding to each signal line electrode.

The display control circuit C0NT forms the display data and its timing signal. That is, in response to the reference clock signal generated by the oscillation circuit O3C, the scan timing signals of the scan electrodes associated with each other and the signal electrodes are supplied to the scan electrode drive circuit R-DRV and the signal electrode drive circuit C-DRV. and a refresh memory RAM address signal, which will be described later. The display data read out according to this address signal is subjected to predetermined information processing as described later to form display data to be supplied to the signal electrode drive circuit C-DRV. In addition,
As described later, the display control circuit C0NT is a so-called character generator (pattern generator) that receives an 8-bit ASCII code and converts it into pixel data of characters and numbers consisting of 5 x 7 dots, although it is not particularly limited. circuit).

The refresh memory RAM stores pixel data such as character code signals or graphics corresponding to display characters to be displayed on the liquid crystal display panel. That is, by repeatedly performing the display according to the character code or graphic data written in the refresh memory RAM, the liquid crystal panel LCD is caused to perform a predetermined display.

In this embodiment, when displaying a figure, characters are often inserted to explain the figure, so in order to easily form composite display data of both, the refresh memory RAM has a text information area and a figure information area. Area 2
The memory area is divided into Note that, although not particularly limited, this refresh memory RAM has a read-only output terminal, and is configured to read data independently of writing/reading from a microprocessor CPU or the like.

FIG. 2 shows a block diagram of an embodiment of the display control circuit C0NT.

In this embodiment, although not particularly limited, the address counter ADC receives the reference clock signal φ and counts it to form an address signal for the refresh memory RAM. As described above, in order to form an address signal that alternately designates the two divided memory areas, the most significant bit of the address signal is determined by the reference clock signal φ. That is, by adding the reference clock signal φ as the most significant bit of the address signal formed by the address counter ADC, for example, as shown in the timing diagram of FIG. 1”
), an address signal designating a memory area in which character information is written is formed. The character code signal read and extracted by the address signal A21 thus formed is, for example, synchronized with the falling edge of the reference clock signal φ to the latch circuit (register) R2.
is maintained. The output signal of this latch circuit R2 is supplied to the pattern generation circuit ROM and converted into the character dot information. On the other hand, in the second half of the cycle when the reference clock signal φ is at a low level (logical "0"), an address signal is formed that specifies a memory area in which graphic information is written. The graphic information read out by the address signal All thus formed is sent to the latch circuit (not shown) in synchronization with the rising edge of the reference clock signal φ.
i register) is held in R1. Thereafter, since the address counter ADC performs a +1 counting operation every cycle of the reference clock signal φ, it is sequentially incremented each time the reference clock signal φ arrives (A22.A12 and A23.A13.
. . ) to form address signals that alternately select the divided memory areas.

In the second half period, the pattern generation circuit ROM converts the character code information into a character pattern signal while the graphic information is being read. Although not particularly limited, in the next read period, the character pattern signal and the graphic signal are combined by passing through an OR gate circuit G and are serially transmitted to the signal electrode drive circuit C-D.
This is what is supplied to the RV. Note that the timing signal CL shown in FIG. 3 is a timing indicating one display section, and although not shown, a shift clock signal of 81 m is generated during this period, and the read display data is serially sent out.

〔effect〕

(1) The display control circuit generates an address signal that alternately designates the character information area and the graphic information area of the refresh memory and reads out the display information of each,
A simple configuration in which these are synthesized using an OR circuit or the like and output, provides the effect that characters and figures can be displayed simultaneously.

(2) By combining the output signal of the address counter and its input clock signal, it is possible to easily generate an address signal that alternately specifies the character information area and the graphic information area of the refresh memory. It will be done.

(3) According to (2) above, it is possible to obtain the effect that address management of the refresh memory can be extremely easily performed.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, the address signal specifying the two memory areas mentioned above may use the person's kakurofuku signal as the least significant bit of the output signal of the address counter.Also, the address signal specifying the two memory areas may use the person's kakurofuku signal. For example, a function may be added to the blue circuit that displays text or graphics preferentially.For example, if there are display characters in that display section, graphic information may be forcibly masked. The RAM and/or signal electrode drive circuit C-DR as the refresh memory may be added with a function of performing the above-mentioned refresh memory or vice versa.
V may be built into the display control device C0NT. Moreover, conversely, each circuit block formed in the display control circuit C0NT may be configured as an independent semiconductor integrated circuit device by a predetermined combination.

[Application field]

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to a display device using a dot-structured liquid crystal display panel, which is the field of application that is the background of the invention, but the invention is limited to this. 1
Oh, )-i? Good 3, good equipment 7. Yo,
. It can be widely used in various display devices that display characters and graphics according to a predetermined timing, such as those using a three-dimensional cathode ray tube.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the display control circuit, and FIG. 3 is an operation of the display control circuit shown in FIG. FIG. LCD...Liquid crystal display panel, R-DRV...Scanning electrode drive circuit, C0NT...Display control circuit, C-DRV...Signal electrode drive circuit, ROM...Pattern generation circuit (read-only memory), RAM...・Refresh memory (random access memory), ADC... address counter, R1, R2... latch circuit (register) ゛ Figure 1 Figure 2

Claims (1)

[Claims] 1. A refresh memory that stores character or graphic information to be displayed, a memory area that stores encoded character information, and a memory area that stores dot-structure graphic information. an address generation circuit that alternately generates an address signal for the refresh memory, a pair of latch circuits that hold the character information and graphic information read out by the address signal at respective timings, and a latch that holds the character information. A display consisting of a pattern generation circuit that receives information held by the circuit and converts it into a dot-structured character pattern signal, and a signal synthesis circuit that synthesizes the output signal of the latch circuit that holds the graphic information and the output signal of the pattern generation circuit. A display control device comprising a control circuit. 2. The display control device according to claim 1, wherein the display device is a liquid crystal display panel having a dot matrix structure and comprising scanning electrodes and signal electrodes. 3. Claim 1, characterized in that the display control circuit is constituted by a one-chip semiconductor integrated circuit, and the pattern generation circuit is constituted by a ROM.
Or the display control device according to item 2.