JPS60229094A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to display devices, and particularly to synchronization of display control controllers that operate independently in a display device using a plurality of display control controllers. It is something.

[Background of the invention]

In recent years, the display systems of personal computers have been required to have higher functionality, and by making good use of the limited functions of a single-chip central processing unit (microprocessor, hereafter abbreviated as MPU), high-speed processing and High-definition display has been achieved.

With this increase in definition, it is inevitable that display functions will be diversified.

In response to this demand, when considering business use or document creation, a kanji display function is essential.

Another important function is dot-by-dot superimposition of the graphic screen and text screen.

Based on this background, as a means to realize kanji display, a graphic display method in which kanji fonts are stored as 11 data in the display memory and displayed, and a graphic display method in which character codes are stored as data in the display memory. , a ROM (hereinafter abbreviated as CG) called a character generator (hereinafter abbreviated as CG).
There is a text display method that uses READ 0NLY MEMORY) for display. The former method has the disadvantage that display processing, for example scroll processing, cannot be performed at high speed. Therefore, in order to speed up the display of geography, it is necessary to display kanji using the latter method. However, when the kanji CGt- is applied to a conventional display device, a drawback arises in that the character spacing becomes narrow. The present invention is a display device devised to eliminate such drawbacks. Therefore, prior to explaining the present invention, the prior art and its drawbacks will be explained using FIGS. 1 to 6.

FIG. 1 is a block diagram of a conventional display system circuit in a personal computer beater. 1 is an MPU, a 2u address bus, 3 is a data bus, and 4 is a reading control signal (hereinafter referred to as R/ (referred to as the IF' line). Further, 5 is an address decoder that decodes the addresses of the circuits necessary for display, and 6 is a CRT (CathoeLg Ray Tu) that generates various timing signals for display.
bs) control circuit (hereinafter referred to as CRTC), 7 is MP
This is a multiplexer that switches between the U address bus 2, the R/M' line 4, and the display address signal line 8 and rask address signal line 9 from the CRTC 6 using a signal supplied by the display timing signal line 10. Furthermore, 111 is a graphic display memory, 12 is a text display memory, and 15 is a memory for displaying graphics.
and 14 are 8-bit etch type latch circuits, and 15 is a CG.

Further, 16 is a composite R1W line that indicates a reading operation to the display memories 11 and 12, 17 and 18 are parallel-to-serial conversion circuits that convert into signals that can be input to the display unit 19, and 20 is a superimposition control of text display and graphic display. The circuit 21 is a timing generation circuit 22 that generates a character-by-character clock (hereinafter referred to as CCLK) and a signal (hereinafter referred to as LOAD signal) instructing the parallel-to-serial conversion circuits 17 and 18 to take in data. is the ccLx signal, 23 is the L0AK) signal line, and 24 is a hard reset circuit.

Also, Fig. 2 is a time chart showing the operation of the display system circuit shown in Fig. 1, Fig. 3 is a time chart of various signals output by cxrc6, Fig. 4 is the content of CG, and Fig. 5 is the kanji character. The display screen, FIG. 6, is a map of the graphics display memory.

In Fig. 1, it is assumed that M-PUl handles data in units of 1Eytt (hereinafter abbreviated as B) and 8 bits, and in this case, the display memories 11 and 12 are memories in units of B. It is a block. Furthermore, the display memories 11 and 12 have a storage capacity sufficient to display one screen tp. As a specific example, if we consider a high-definition graphic display of 640 dots in the horizontal direction and 400 dots in the vertical direction, the graphic display memory 11 will need a storage capacity of 52 KB. [For example, the display memory 11 is 16f
hit RA M (Random Access M
memory ) can be configured using 16 pieces. Furthermore, regarding text display, in this conventional example, the character font is 8 dots x 16 dots, so the display screen is 80 characters x 25 lines, and the text display memory 12
can be configured using one 2KE RAM. Also,
The MPU 1 reads and writes display data to and from the display memories 11 and 12, and inputs and outputs data using addresses designated via the address bus 2 and the data bus 3. At this time, a signal indicating the input/output direction of this data is output to the R1W line 4. The multiplexer 7 is switched by the signal supplied by the display timing signal line 9, and sends the composite address signal and composite R/F signal for driving the display memory 11.12 to the composite address bus 25 and the composite R1W line 16. Output to. Furthermore, the MPU 1 sets necessary information in the CRTC 6 using the decode signal outputted by the address decoder 5 and the data bus 3. As a result, C
The RTC 6 receives C from the timing generation circuit 21.
Various timing signals synchronized with CLK are output at timings corresponding to information set by the MPU. CRTC6
The signals output by will be explained later using FIG.

Next, the operation of the circuit controlled by the CRTC 6 will be explained using the time chart shown in FIG. First, CRTC
6 outputs a display address and a rask address to a display address signal line B and a rask address signal line 9 in synchronization with CCLX. In response to this, the multiplexer 7 transfers the display memories 11 and 12 via the composite address bus 25.
Drive wo. Here, the text display memory 12 has an access time (tAcl) after inputting the display address.
After ', display data (character code) is output to the latch circuit 14. Timing chart so far)
Shown in Figure 2.

In FIG. 2, the period of CCLK is 400 f&sec, and the access time of the text display memory 12 is 150 lsec. Furthermore, the display addresses φ, 1, 2, . . . shown in FIG.
The data regarding the text display corresponding to 5... are shown as TI, TI, 7'2....

Returning to FIG. 1 again, the latch circuit 14 extends the display data k 400 n seconds, which has been output for only 2503 seconds. The expanded data is given to the CG 15 together with the rusk address output by the CRTC 6. For detailed explanations regarding the rusk address and CG15, see Figures 3 and 4.
This will be explained later using figures. In response to this, C.
G15 outputs display pattern data after an access time (tAC2)f. Display pattern data is LOA
While the D signal is low, it is taken into the parallel-to-serial conversion circuit 18. The timing chart up to this point is shown in FIG. In FIG. 2, the access time for CG 15 is 250 seconds. Here, assuming that the latch circuit 14 did not exist, the output determination time of (:'G15) would be 44 seconds.For this reason, the latch circuit 14 is necessary.On the other hand, the graphic display memory 11 Display data (display pattern) is output after an access time (tAc5)f has elapsed since the address was input.

In response to this, the latch circuit 13 latches at the same timing as the latch circuit 14. Furthermore, uh.

The checked display pattern data is taken into the parallel-to-serial conversion circuit 17 at the same timing as the parallel-to-serial conversion circuit 18. The timing chart up to this point is shown in FIG. In addition, in FIG. 2, the access time of the graphic display memory 11 is 100 seconds, and the display addresses φ, 1,
2. Data regarding graphic display corresponding to ...... is available from TI.

It is indicated as TI, r2... Here, if it is assumed that the latch circuit 13 is not provided, the text display pattern data and the graphic display pattern data do not correspond to the LOAD signal. Returning to FIG. 1 again, the visible information output by the parallel-to-serial conversion circuits 17 and 18 is selected by the superimposition control circuit 20 and output to the display section 19.

Next, FIG. 3 will be explained. Figure 3 shows CRTC6
This shows a time chart of display addresses and rask addresses output by . Display addresses are output from φ to 79 in synchronization with CCLK. This period is 1 rusk,
In other words, it corresponds to one horizontal line on the display screen. Therefore, 16 rasters correspond to one line on the display screen, and the display address repeats from φ to 79 times between each raster. Furthermore, when the rusk address finishes one line of karantra,
Return to φ again and start Karantra for one line. On the other hand, the count range of the display address changes from 8φ to 159. After performing the same operation for 25 lines, the process is returned to the initial state and the same operation is repeated again.

Further, the operation of the CG 15 will be explained using FIG. Figure 4 shows the contents of the CG. In particular, the character code (here I will show the ASCII code) is $41.
(Hereinafter, a $ mark is added at the beginning to indicate that it is a hexadecimal number.) This is the rAJ character font. Therefore, if the character code imported by CG15 is $41 and the raster address at that time is 7, $42 will be displayed as pattern data, and if the raster address is 8, $7E will be displayed from CG15. Output.

If a kanji CG with a 16 dot x 16 dot font is used in the display circuit described above, the quality of the display screen will deteriorate as shown in FIG. 5(a). Tsumashi,
If the kanji ``A'' and the kanji ``富'' are displayed vertically side by side, there will be no space between the characters. Therefore, as shown in FIG. 5(A), it is required to display each character stroke in a 2o raster. In response to this requirement, when 20 raster display is performed using a conventional display system circuit, there are the following drawbacks.

The symbol (-) in FIG. 6 indicates the memory allocation of the graphic display memory 11 shown in FIG. Damn, 52768
The memory space of B is a raster address, 16 (= 2')
It is divided. The memory required to display one raster is 2K.
E, there is an unused area of 48B per raster, and a total of 768B of unused area. On the contrary,
Figure 6<h shows the memory allocation for 20 raster display.
> is. In this case, due to the structure of the memory, 20 divisions are not possible, so 32 (=25) divisions are required. Therefore, 65556E of memory space is required! 020
Since it is a raster, the memory required for one raster is 1.6KB.
The unused area is 448B. Further, since the divided area from the 20th raster to the 31st raster is completely unused, there is a total of 33556B of unused area. In short, if the text display size is 20 rasks, twice the capacity of the graphics display memory is required, and moreover, more than half of the total capacity is not used.

Therefore, in order to eliminate the above-mentioned drawbacks, it is conceivable to provide a graphic CRTCf that controls 16 raster display and a text CRTCf that controls 20 raster display. Tsumashi, method of using two CRTCs, 7th
The method will be explained using figures. Figure 7 is cxrc meeting 2
In this figure, circuit blocks having the same functions as those in FIG. 1 are given the same symbols.

Further, in the same figure, 26 is a CRT.

A 27-digit multiplexer is required, whereas the conventional CRTC6 is a 16-digit multiplexer.
The CRTC26 newly installed multiplexer 2 to control only the raster display and digital graphic display.
2o raster display and straight text display are controlled through 7. In short, with this kind of circuit configuration, 16
It is possible to display a raster display screen and a 20-raster display screen in an overlapping manner, and it is possible to solve the drawback that display memory cannot be used effectively. However, in the display system circuit shown in FIG. 7, the CRTC 6 and CRTC 26 operate asynchronously, resulting in the following drawbacks.

Immediately after receiving the display address and raster address count information t-MPU1, the CRTC 6 starts outputting the display address and raster address. Therefore, at system startup, CRTC6 and CRr C2
It is impossible to start the operation at the time of the 6th shift, and the display screen (graphic screen) controlled by c-4c6 and the display screen (text screen) controlled by the CRTC 26 cannot be synchronized. For this reason, as shown in FIG. 8(a), there is a misalignment between the text screen and the graphic screen, resulting in a disadvantage that the normal display shown in FIG. 8(A) cannot be obtained.

[Purpose of the invention]

An object of the present invention is to provide a means for adjusting the phase of signals output by a plurality of CRTCs in a display device using a plurality of CRTCs, in order to eliminate such drawbacks of the prior art.
The object of the present invention is to provide a circuit for controlling CRTC' (il-).

[Summary of the invention]

In order to achieve the above object, the present invention provides a phase detection circuit that detects a phase shift of multiple signals and a reset circuit that generates a reset signal of an arbitrary phase, and when the phase detection circuit detects a phase shift, , a reset circuit operates, and a plurality of CRTCs can operate in any phase according to the reset signal.

[Embodiments of the invention]

In this example, in a display system circuit using two CRTCfs devised to realize overlapping of a text display and a graphic display with different numbers of rasters, the text display screen and the graphic display screen are The phase adjustment is performed by detecting the deviation of the display timing signal using a display timing signal and resetting the CRTC.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 9 shows an embodiment of the present invention, in which a circuit block having the same function as that in FIG.
The same reference numerals as in the figure are given.

In FIG. 9, 30 is a composite address signal line, 31 is a composite R/W signal line, and 32 is a raster address signal line from the CRT C26. Furthermore, 33 is a phase control circuit 1;
4 is a reset signal line from the hard reset circuit 24, 3
5 is a vertical synchronizing signal line from the CRTC 26, and 36 and 37 are reset signal lines for controlling the CRTC 6 and CRTC 26, respectively. In addition to FIG. 9, FIGS. 10 and 11 are examples of detailed configurations of the multiplexers 7 and 27, respectively. Further, FIG. 12 is a detailed configuration diagram of the phase control circuit 3S, and FIGS. 13 to 17 are time charts for explaining the entire circuit of FIG. 12.

First, the operation of the circuit shown in FIG. 9 will be explained.

Conventionally, a composite address bus 25 and a composite R/W+1i! 16
In this case, only the graphic display memory 11 is fully driven. Therefore, the CRTC 6 controls the graphic display.

Hereinafter, the CRTC 6 will be referred to as a graphic CRTC. In addition, the conventional graphic display memory 11
Since the latch circuit that existed between the parallel and serial conversion circuit 17 is no longer present, the display data output from the graphic display memory 11 is taken directly into the parallel to serial conversion circuit. In contrast to graphic display, text display is CRTC2
6 performs display control, the CRTC 26 will hereinafter be referred to as a text CRTC. The text display CRTC 26 outputs a display address and a rask address to the full display address signal line 28 and raster address signal line 32 in synchronization with CCLK. In response to this, multiplexer 27 drives text display memo 1712tl via composite address bus 30. The operation after the text display memory 12 takes in the display address is the same as that shown in FIG. The MPU 1 is also capable of reading and writing data to and from the text display memory 12, and inputs and outputs data at a specified address via the address bus 2 and via the data bus 3. At this time, R/IF' line 4
A signal indicating the input/output direction of this data is output.

In response to this, the multiplexer 27 outputs a composite R/II' signal for driving the text display memory 12 to the composite R/F signal line 31. Furthermore, the MPU 1 uses the decode signal output from the address decoder 5 and the data bus 5 to set necessary information in the text CRTC 26. Here, all the differences between the multiplexers 7 and 27 will be explained below using FIGS. 10 and 11.

First, FIG. 10 shows the multiplexer 7, and the same circuit blocks and signal lines as in FIG. 9 are given the same symbols. In Fig. 10, 51 is a graphic CRTC
6 is a signal line consisting of a display address signal line B and a raster address signal line 9, and 50 is a selector that switches between the address bus 2, the signal line 51, and the display timing signal line 10. As will be described in detail later, the display timing signal line 1
0 indicates a display period when it is at a high level, and a non-display period when it is at a low level. Therefore, when the display timing signal line 10 is at a high level, the selector 51 determines whether the signal line 51?
+-, selects two address buses when at low level. Here, for address bus 2 and signal line 51, 1,414
corresponds to RA'5, AlB to R,42, and Aφ to HAφ.

Furthermore, the composite address signal line 25 is only 15 bits, making it possible to create a memory space of 52 KN required for a graphic display memory. In addition, composite RAW' signal line 1
6 is a display period (display timing signal 10 is in a high state)
(high state) during the non-display period, R1W
Indicates the condition of the line.

Next, FIG. 11 will be explained. FIG. 11 shows the multiplexer 27, and the same circuit blocks and signal lines as in FIG. 9 are given the same symbols. In Figure 11, 60
is a selector; when the display timing signal line 29 is at a high level, the display address signal line 28 is selected, and when the display timing signal line 29 is at a low level, the address bus 2 is selected.

Here, regarding display address signal line 2 and address bus 2, MAv6 is A7, MA9 is A9. ,,,,,,
,.

Each corresponds to MAgke and A〆. Further, the composite address signal line 50 has only 11 pits, which can create the 2 KB memory space required for the text display memory.

Further, the composite R/II' signal line 31 is similar to the composite R/W signal line 16. In short, the multiplexer 7 outputs a total of 15 bits of address information, 11 bits of the display address and 4 bits of the raster address outputted by the graphic CRTC 6, to the composite address signal line 25, whereas the multiplexer 27 outputs the address information of the text card CRTC 26 The difference is that only 11 bits of the display address to be output are output to the composite address signal line 30.

Returning again to FIG. 9, the operation of the phase control circuit 33, which is most important in the present invention, will be described below. In this embodiment, the phase control circuit 36 firstly controls the graphics C.
The phase shift between the display timing signal on the display timing signal line 10 from the RTC 6 and the display timing signal on the display timing signal line 29 from the text CRTC 24 is detected.

At this time, the sampling clock for detecting the phase shift is C
CCLK supplied by the CLK signal line 22, and
A vertical synchronizing signal is supplied through a vertical synchronizing signal line 35 and controlled by a vertical synchronizing signal so that phase shift detection is performed only once per one screen scan. Then, if a phase shift is detected,
The phase control circuit 33 performs phase adjustment on the graphic CRTC 6 and the text CRTC 7-6 using reset signals on the reset signal lines 56 and 37. Further, the phase control circuit 33 receives a reset signal from the hard reset circuit 24 (1), and performs CETC6 and CETC260 phase adjustment, reset, and reset.

In this embodiment, the phase of the reset signal 1s36 is delayed from the reset signal of the reset signal line 37 by one cycle of CCLK, i.e., 4004 seconds. This will be explained below using FIG. 12.

FIG. 12 is a time chart of the embodiment shown in FIG. In FIG. 12, (cL) is the timing of text display, and (A) is the timing of graphic display. First, at (α), when the reset signal on the reset signal line 37 becomes low level or high level, the text CRTC 26 starts outputting display addresses in order from p. Next, via the negative address signal line 3o,
- The above display address drives the text display memory 12, and display data (character code) is output. moreover,
After the display data is latched by the latch circuit 14,
The parallel-to-serial conversion circuit 18 takes in the display pattern data using the LOAI signal, which is applied to the CG 15 and the display pattern data. On the other hand, in <b>, the reset signal of the reset signal @37 is (α
Similarly to the reset signal υ and (-), the graphics cxrc6 starts outputting the display address.

Next, the display address drives the graphic display memory 11 via the composite address signal line 25 to output display data (display button), and the parallel-to-serial conversion circuit 17 uses the LOAD signal to output the display data. Input (display pattern). In short, by shifting the phases of the reset signals of CRTC6 and 26 by one cycle of CCLK, the addresses corresponding to the display addresses (in Fig. 12, rls and Gll, T1 and G1) indicating the same position on the display screen can be adjusted. Display pattern data can be loaded into each parallel-to-serial conversion circuit at the same timing of the LOAD signal. That is, in the conventional example shown in FIG. 1, by latching the graphic display pattern data, the jilt, L
The phase control circuit 53 replaces the latch circuit 13 which corresponds to the text display pattern data for the 4D signal.

Next, the phase control circuit 35 will be explained in detail using FIG. 13. FIG. 13 is a detailed circuit diagram of the phase control circuit 33, in which circuit blocks having the same functions as those in FIG. 9 and the same signal lines are given the same symbols. In Figure 13, 70
~75fi edge type 7 lip flow circuit (for example, Hitachi TTLHD74L 574A), 76 is a detection signal line that indicates that a phase shift has occurred, 77 is an acknowledge signal line that indicates that a phase shift has been recognized, 78 is a phase shift detection Status signal t79 allowing operation
This is a detection operation signal line indicating that phase detection has been performed. Further, 80 is a phase detection circuit for detecting a phase shift;
A reset generation circuit 82 generates a 1-digit reset signal, and a detection control circuit 82 controls a phase detection circuit. moreover,
83 is an ENOR (Exclusive NOR) circuit,
84 and 85 are OR circuits, and 86, 87 and 88 are inverters. Before explaining the circuit operation, the display timing signal lines 10 and 29 and the vertical synchronization signal will be explained using FIG. FIG. 14 is a time chart of various signals output from the CRTC 26. In FIG. 14, the display timing signal indicates a horizontal scanning period when it is at a high level, and indicates a horizontal scanning retrace period when it is at a low level. In other words, the period between element addresses β to 79 is the horizontal scanning period.

Further, the β to 19 rasters correspond to one line, the e to 19 lines are the vertical scanning period, and the period from the 20th line to the next pth line is the vertical scanning retrace period. Furthermore, during the vertical retrace period, the display timing signal is at a low level. The vertical synchronization signal is output row by row during the vertical scanning retrace period. Here, the 26th line is a vertical synchronizing signal for one line.

On the other hand, since the CRTC 6 outputs 16 raster addresses per row, the vertical synchronization signal is a signal for 16 rasters.

Therefore, it is difficult to detect the phase shift between the CRTCs 4 and 26 using the vertical synchronization signal. Therefore, the phase shift is detected using a display timing signal. The above is the explanation regarding the display timing signal and the vertical synchronization signal, and we will return to the explanation of FIG. 13 again. First, the phase detection circuit 8o
With CCLK as the sampling clock, the display timing signal is sampled using flip-flops (hereinafter abbreviated as FF) 70, 71, and 72, the phase shift is detected by ENOH, and when a phase shift occurs, the detection signal is output. A low level is output on line 76. Here, the display timing signal of the display timing signal line 1o is sampled by the FF 71 and then delayed in phase by the FF 72 because the phase of the graphic CRTC 6 is advanced by one cycle of CCLK. Moreover, when the acknowledge signal line 77 becomes low level,! When F7Q and 72 are at low level, the detection signal line is at high level. That is, the detection operation signal 79 changes from low level to high level at 9 o'clock when either of the display timing signal lines 1o and 29 becomes high level. The detection control circuit 82 is then notified that the phase detection circuit 80 has performed the detection operation. Further, when the status signal line 78 is at a high level, the detection operation will not be performed unless CCLK is turned off. Next, the reset generation circuit 81 sets the reset signal lines 56 and 37 to a high level when the detection signal line 76 is at a high level. A time chart of this state is shown in FIG. 15 (α). FIG. 15(a) shows that the phase difference between the display timing signals of the display timing signal lines 10 and 29 is one cycle of CCLX, and there is no need for phase adjustment, so no reset is performed. Further, in the reset generation circuit 81, when the detection signal line 76 becomes low level, the FF 73 latches the low level, and the acknowledge signal line 77 immediately becomes low, so that the detection signal line 76 becomes high. Therefore, the reset signal line '57 becomes low level for one cycle of CCLK. Furthermore, since the reset signal line 36 is latched by the FF 74, the signal is delayed by one cycle of CCLK. 1st
FIG. 5(A) is a time chart showing these operations. In FIG. 15(A), the phase of the display timing signal line 10 is delayed, a phase shift occurs, and the detection signal line 76 becomes high level, so the reset signal line 37 becomes low level, and at the same time, the acknowledge signal Since the line 77 also goes to low level, the reset takes one cycle of CCLK. Finally, the detection control circuit 82 will be explained. When the detection operation signal line 79 goes from low level to high level, the detection control circuit 82 does not perform the detection operation because the status signal line 78 goes to high level. Next, the detection operation becomes possible when the vertical synchronization signal is output and the FF 75 reaches a low level. Further, the explanation will be made using FIG. 16 showing a time chart of the detection control circuit 82. FIG. 16 shows the display timing signal,
This is a time chart of the vertical synchronization signal and status signal.When the vertical synchronization signal is output, the status signal line 78
goes low, allowing detection operation. Next, when the vertical scanning period begins, a display timing signal is output, so a detection operation is performed and the status signal line 78 becomes low. In other words, as mentioned earlier, it is difficult to detect the phase using the vertical synchronization signal, so the display timing signal is used. It shows a time chart when the signal is output.

FIG. 17 is a time chart of the reset signal lines 54, 56 and 37, and the reset signal is on the reset signal line 34.
When the reset signal line 37 is input, the FF 75 shown in FIG.
and 36 show how the reset signal is output.

An example of the operation of the phase control circuit 330 has been described above, but
This is not limited to the six cases of Kimomoko. For example, in order to detect screen shift, it is possible to use a horizontal synchronization signal output from a CRTC or a decoded signal of a display address and a rask address. In addition, in this implementation, the phase difference of the signal for resetting the CRTC is CCLK
However, this phase difference can be made to have a phase difference of two cycles of CCLK or three cycles of #'i. Furthermore, if the hardware of the phase control circuit 36 is increased,
Phase control of three or more CRTCs can also be realized. There is also a method of controlling a plurality of CETCs by inputting a vertical synchronization signal outputted from the CRTC to a reset generation circuit instead of the phase shift detection signal to apply a reset at a constant cycle. Furthermore, the signal input to the reset generation circuit is not limited to the signal output by the CRTC, but it is also possible to use a constant periodic signal generated by a simple counter circuit.

〔Effect of the invention〕

As described above, according to the present invention, since it is possible to control the phase of a plurality of CRTCs, it is possible to display each display screen in a blended manner without causing any deviation between display screens having different numbers of rasters. effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional example of a personal computer beater display system circuit, Fig. 2 is a timing diagram related to the display data processing shown in Fig. 1, and Fig. 3 is a timing diagram of signals output by the CRTC. The block diagram of the embodiment, FIG. 10 and FIG. 11 are as follows. A detailed configuration diagram of the multiplexers 7 and 27, FIG. 12 is a timing diagram related to display data processing in FIG. 9, FIG. 13 is a detailed circuit diagram of the phase control circuit 66, and FIG. 14 is a JdCRT.
Timing diagrams of signals output by C. FIGS. 15, 16, and 17 are timing diagrams showing the operation of FIG. 13. 6... CRT for graphic display C26... CRTC for text display 55... Phase control circuit 80... Phase detection circuit 81
... Reset generation circuit 82 ... Detection control circuit
Z figure LOA signal 3rd figure 4th figure 5th figure $ et al figure raster c'no qfI? l Fig. 11 Fig. 1z (cL) (b) 伽Data (l#, putter〉) Hill φ qtLOAf) Signal Fig. 13 Fig. 14. ccctk]]11FU1JT---flfU1f
LnJL---JIJLrL stem! 5 Figure (0-) 3θ Cb) 9 Continuation of the first page @ Inventor Hiroyuki Mano 0 Inventor Takeshi Shiohara 29 Akiji, Yoshida-cho, Totsuka-ku, Yokohama City, Hitachi, Ltd., Microelectronics Equipment Development Laboratory, Yokohama 292i Yoshida-cho, Totsuka-ku, Hitachi Video Engineering Co., Ltd.

Claims (1)

[Claims] 1. A first memory for displaying a graphic screen, a cathode ray tube controller for graphics that controls reading of the first memory, a second memory for displaying a text screen, and a second memory for displaying a text screen; In a display device having a text cathode ray tube controller that controls reading of a second memory, a first display timing signal output from the graphic cathode ray tube controller and a first display timing signal output from the text cathode ray tube controller. a phase detection means for detecting a shift in the low phase of the second display timing signal; and a reset signal for supplying a reset signal to the graphic cathode ray tube controller and the text cathode ray tube controller according to the output of the phase detection means. A display device comprising a generating means. 2. The display device according to claim 1, wherein the phase detection means performs phase detection once in one vertical scanning period.