JPH02131289A - Clock skew adjusting circuit for synchronized system - Google Patents

Abstract

PURPOSE:To synchronize the system by detecting the phase difference between the output signals of control circuits and adjusting the phases of the clocks of the control circuits according to the phase difference. CONSTITUTION:A dot signal VDTM from a display control circuit 4a is inputted to the display control circuit 4a again as a phase data signal PDT for phase comparison. Further, a dot clock DCKS from a display control circuit 5 is inputted to the display control circuit 4a as a phase clock PCK for phase comparison. The clock skew adjusting circuit 10 delays a master clock MCK supplied from an oscillator by a delay circuit 11 and supplies it as an internal clock CLK to respective parts of the display control circuit 4a. Here, the delay quantity of the delay circuit 11 can be adjusted with a control signal and the phase adjustment between the display control circuits 4a and 5 is enabled. Consequently, the system is synchronized normally.

Description

[Detailed description of the invention]

"Industrial Application Field" The present invention relates to a clock skew adjustment circuit that is used in a synchronization system and synchronizes the entire system by adjusting the clock phase of each circuit constituting the system. ``Prior Art'' In personal computers and the like, systems that can display multiple screens in a superimposed manner have been realized. This type of system is equipped with a plurality of display control circuits, and superimposed display of screens is performed based on output signals from each display control circuit. Furthermore, in this system, each display control circuit is synchronized in order to perform normal screen overlapping display. FIG. 7 is a block diagram showing the configuration of a conventional screen overlay system. l is the CPU that controls the entire system (
It is a central processing unit) and sends and receives data to and from each unit via the common bus CB. Reference numeral 2 denotes a RAM, which temporarily stores data processed by the CPUI. 3 is RO
M, and the control program for this system is stored. 4 and 5 are display control circuits. These display control circuits 4 and 5 have a video RAM and a kanji 10
M (both not shown) are connected. In these display control circuits 4 and 5, lighting control information for each dot that makes up the display screen is created based on the control of the CPUI, and for each dot, a color code or dot that specifies the display color of the dot is created. In addition to being output as a signal, a dot clock synchronized with the dot signal is also output. A priority switching circuit 6 selects each output signal of the display control circuits 4 and 5 according to its respective priority, and supplies the selected signal to the display device 7. In this system, the output signal of the display control circuit 4 is given priority. Therefore,
The display control circuit 4 is a mask display control circuit, and the display control circuit 5 is a mask display control circuit.
is called a slave display control circuit. FIG. 8 is a block diagram showing the configuration of display control circuits 4 and 5 and priority switching circuit 6 in FIG. 7. The output signal of the onler OSC is input to the display control circuit 5 as a mask clock. Further, the output signal of the oscillator OSC is delayed by a delay circuit 4D and inputted to the display control circuit 4 as a master clock. Here, the delay time of the delay circuit 4D can be changed by a control signal from the CPU I. Note that the role of this delay circuit 4D will be described later. The display control circuit 4 outputs a dot signal VD for each dot constituting the display screen.
TM and a dot clock DCKM synchronized with this are output. Here, when the dots to be displayed are transparent, all bits of the color code in the dot signal are "0". Similarly, from the display control circuit 5, the dot signal VDT
S and a dot clock DCKS synchronized with this are output. Further, by sending a horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC from the display control circuit 5 to the display control circuit 4, each display control circuit is synchronized in units of dots. The priority switching circuit 6 includes registers 6a and 6b, a selector 6c, an SOR gate 6d, and a register 6e. The dot signals V D TM and V D 'l' S are supplied as input data to the renostars 6a and 6b, respectively. Furthermore, the dot clock DCKS is commonly supplied as a clock signal to the registers 6a and 6b. Then, at the rising edge of dot clock DCKS, dot signals VDTM and VDTS are read into registers 6a and 6b, respectively. The output signals of all bits of register 6a are input to OR gate 6d. When these output signal levels are all “0”, that is, when the display dots are transparent, O
The output level of the R gate 6d becomes "0". Selector 6
c is switched by OR gate 6d. and,
When the output level of the OR gate 6d is "0", the register 6a is selected, and when the output level is "1", the register 6b is selected.
The output signal of the selected register is input to the register 6e. Register 6e outputs input data to dot clock DCKS.
It is read at the timing of the rising edge of , and is output to the display device 7. In this way, in this priority switching circuit 6, the dot signal VDTS of the slave display control circuit 5 is selected when the display color of the dot signal VDTM output from the mask display control circuit 4 is transparent, and the dot signal VDTS of the slave display control circuit 5 is selected. In this case, the dot signal VDTM output from the mask display control circuit 4 is selected and input to the display device 7. As a result, the display device 7
The two screens are displayed superimposed on each other. Now, in this screen overlapping system, the dot signals VDTM and V output from the display control devices 4 and 5 are
DTS is connected to register 6a by a common clock DCKS.
and 6b. however,
The display control circuits 4 and 5 have different signal transmission delay times due to manufacturing variations in the elements, and even if they are driven by a common master clock, the output signals VDTM and DCKM
and the output signals VDTS and DCKS, the timings at which the signals change may be significantly different from each other. especially,
This tendency is particularly pronounced when the display control circuits 4 and 5 are implemented using separate LSI chips. Therefore, the problem described below occurs. FIG. 9 is a time chart showing various phase relationships between signals VDTM and DCKM and signals VDTS and DCKM. In the display control circuit 4 of FIG. 8, the dot signal V
The contents of the DTM are switched to MO, M1, M2, etc. in synchronization with the rising edge of the dot clock DCKM. In addition, in the display control circuit 5, the dot signal VDT
S is synchronized with the rise of the dot clock DCKS,
The contents are switched to SO, S1, 82 and so on. Now, if the phase of each output signal is in the relationship as shown in (a), for example, the double clock DC indicated by diagonal lines in FIG.
At the rise of KS, data M1 and S1 are read into Renostar 6th and 6b, respectively. Therefore, in such a phase relationship, normal overlapping display is performed on the display device 7. However, as in the case (b), if the phase relationship is such that the dot clock DCKS rises near the point in time when the dot signal VDTM is switched, the data reading operation in the subsequent register 6a becomes extremely unstable. That is, due to the jitter of each output signal during operation, for example, at the rise of the diagonally shaded dot clock DCKS, data M1 is read into the register 6a and data M2 is read into the register 6a, resulting in a very unstable state. . Therefore, in such a phase relationship,
Normal overlapping display is not performed on the display device 7. As described above, due to variations in the signal delay times of the display control circuits 4 and 5, there is a possibility that normal overlapping display will not be performed. In this case, master clock MCK
By making the cycle sufficiently large, it is possible to avoid being affected by the phase difference between each double clock, but this will reduce the system speed and make it impossible to satisfy the required performance. It ends up. Therefore, in the conventional screen overlay system, the 8th
As shown in the figure, the display control circuit 4 is controlled by the delay circuit 4D.
The phase difference between the master clocks MCK and 5 is adjusted. By doing this, the phase difference between the dot signals VDTM and VDTS is adjusted so that only data corresponding to the same dot is read into the registers 6a and 6b. "Problem to be solved by the invention" By the way, the conventional screen overlay system described above is
It is necessary to attach a delay circuit externally to the display control circuit, which increases the number of parts. In addition, each time one system was manufactured, it was necessary to check the phases of the output signals of the display control devices 4 and 5 and adjust the delay amount of the delay circuit 4D to ensure normal operation. The process was included in the manufacturing process. Therefore, there was a problem in that the manufacturing cost increased. This invention was made in view of the above-mentioned circumstances, and in a synchronization system such as the above-mentioned screen superimposition system, it automatically adjusts the phase of the clock of each circuit making up the system and synchronizes the system. It is an object of the present invention to provide a clock skew adjustment device that allows the clock skew adjustment to be performed. "Means for Solving the Problems - 1 In order to solve the above problems, the first invention has a plurality of control circuits that are driven by a clock and output data signals synchronized with the clocks, and the control circuits of these control circuits. A synchronization system that performs synchronization based on each output signal, comprising: a phase detection means for detecting a phase difference between each output signal in the plurality of control circuits; and a phase detection means for detecting a phase difference between each output signal in the plurality of control circuits; A second aspect of the present invention is a display that is driven by a clock and outputs a dot signal constituting a display screen and a dot clock synchronized with the dot signal. Has multiple control circuits,
In a screen overlay system that displays multiple screens overlappingly on a display device based on dot signals and dot clocks output from these display control circuits, Moeki calculates the phase difference between the output signals of multiple display control circuits. The present invention is characterized by comprising: a phase detection means for detecting the clock; and a clock skew adjustment means for adjusting the phase of the clock of each display control circuit according to the phase difference. Further, in a third invention, the phase detection means in the second invention detects a phase difference between a dot clock in a specific display control circuit among the plurality of display control circuits and a dot signal in another display control circuit. It is characterized by Further, a fourth invention is characterized in that the phase detection means in the second invention detects a phase difference between each dot clock outputted from the plurality of display control circuits. "Operation" According to each of the above configurations, the phase detection means detects the phase difference between the output signals of each control circuit. Based on this detection result, the clock phase of each control circuit is adjusted. As a result, the phases of the output signals of each control circuit are adjusted, and the system is properly synchronized. "Example" Hereinafter, an example of the present invention will be described with reference to the drawings.

[Example I]

FIG. 1 is a block diagram of a clock skew adjustment circuit 10 according to a first embodiment of the present invention, and FIG. 2 is a screen superimposition system using a display control circuit 4a incorporating the same circuit 10 as a mask display control circuit. FIG. In addition, in FIG. 2, parts corresponding to those in FIG. 8 described above are given the same reference numerals. In the screen superimposition system shown in FIG. 2, the dot signal VDTM output from the display control circuit 4a is re-inputted to the display control circuit 4a as a phase data signal PDT for phase comparison. Further, the dot clock DCKS output from the display control circuit 5 is manually inputted to the display control circuit 4a as a phase clock PCK for phase comparison. In the clock skew adjustment circuit lO shown in FIG.
Mask clock MCK supplied from oscillator OSC
is delayed by the delay circuit 11, and the internal clock CL
The signal K is supplied to each part of the display control circuit 4a. Each part of the display control circuit 4a uses this internal clock CLK.
operates in sync with Here, the delay circuit 11 has a configuration in which the amount of delay can be adjusted by a control signal. Therefore, the display control circuit 4a and the display control circuit 5
It is possible to adjust the phase with In the screen overlay system of FIG. 2, when initialization is performed, a clock skew adjustment mode is executed as the final operating mode. In this mode, the test signal 'r S T h<“1” input to the selector l2
Then, the test pattern T D 'I'' output from the test pattern generation circuit l3 is outputted as a dot signal V l) T M via the selector II and the buffer l3.Then, the phase detection circuit 15 generates the dot signal V D TM and the dot clock D of the display control circuit 5
A phase difference with CKS is detected, and a detection signal ER corresponding to the phase difference is output. Then, this detection signal ER is taken into the resultant deafness display circuit I6 by the internal clock CLK. Then, in the result status display circuit 16, the dot signal VDT
It is determined from the detection signal ER whether or not M and the dot clock DCKS satisfy a predetermined phase relationship, and if not, an error signal ERST is output. When the delay amount of the delay circuit It is changed, the dot signal VD
The phase of TM changes accordingly. Therefore, the phase difference between the dot clock DCKS and the dot signal VDTM output from the display control circuit 5 changes. In this clock skew adjustment circuit lO, the delay circuit If
Internal clock C
The phase of LK is switched, and the presence or absence of the error signal ERST is checked for each phase condition. Then, a stable internal clock phase in which no error signal ERS'r is output is searched for. When the phase adjustment of the internal clock CLK is completed as described above, the screen superimposition system enters the normal display mode. In the normal display mode, the test signal TST is "0". Then, the color code of each dot constituting the display screen is read out one dot at a time from the dot data generation circuit 17 in synchronization with the internal clock CLK, and this is read out from the dot data generation circuit 17 in synchronization with the internal clock CLK.
2 and buffer l4, it is output as a dosoto signal VDTM. Note that the internal clock CLK is buffer 1.
8 as a dot clock DCKM, but this dot clock DCKM is not used in the screen superimposition system of FIG. Next, a specific example of the above-described clock skew adjustment circuit IO will be explained. FIG. 3 is a circuit diagram showing a specific example of the cross skew adjustment circuit 10, and FIG. 4 is a time chart showing the operation of the circuit shown in FIG. In order to clarify which circuit in FIG. 3 each block in FIG. 1 corresponds to, the symbols assigned to each block in FIG.
It is attached to the corresponding circuit in FIG. The operation of this circuit will be explained below. In the screen overlay system, when the clock skew adjustment mode is initiated, control data D1'B is provided. This control data DTB is written into register lla by write signal WCS. And register l
The fourth bit output of la (“1” in this case) is supplied to test pattern generation circuit summer 3 and selector 12 as test signal TST. Further, the 0th to 2nd bits of the register Ila are sent to the selector lld as the select signal TSO-TS2, and the 3rd bit is sent to the EXO as the signal PSL.
The master clock MCK input from the oscillator OSC (Figures 1 and 2), which is input to the R gate Ilb, passes through the EXOR gate 1lb,
It is manually input to the multi-stage delay gate Ilc. The delayed output of each stage of the multi-stage delay gate llc is supplied to the selector 12. Of these delayed outputs, those corresponding to the select signals TSO to TS2 are selected by the selector ttd and output as the internal clock CLK. In this way, the master clock M C K
An internal clock CLK whose phase is shifted from that of the internal clock CLK is generated. Note that when "1" is output as the signal PSL,
Master clock MCK is inverted and multi-stage delay gate ll
It is manually operated by c. Therefore, in this case, the internal clock CL
The phase of K is further shifted by half a period. When the test signal TST is "0", the output of the AND gate 13a in the test pattern generation circuit 13 is "0"
Therefore, "0" is output from the flip-flop 13b. Then, when the test signal TS'r becomes "summer", the previous Q output is read as manual data in the flip-flop 13b, and the internal clock CL
A toggle operation synchronized with K is started. As shown in FIG. 4, the flip-flop 13b generates a test pattern TDT that alternately repeats "l" and "0" each time the internal clock CLK rises. ”, this test pattern TDT is selected and output by the selector 12. Then, the output signal is input to the buffer I4, and at the next rise of the internal clock CLK, the first bit signal VDT. This signal VDT. is inputted as a phase data signal PDT to the data input terminal D of the flip-flop 15a in the phase detection circuit 15. On the other hand, the clock input terminal of this flip-flop 15a is inputted to the display control terminal D. The dot clock DCKS of the circuit 5 is input as the phase clock PCK.The phase data signal PDT is read into the flip-flop 15a by this phase clock PCK, and is output as the signal RDT from the flip-flop 15a in synchronization with the rising edge of the phase clock PCK. Then, this signal RDT is inputted to one input terminal of EXOR gate +5b.Here, EXOR gate 1
The signal TDT is input to the other input terminal of 5b. Then, the EXOR gate 15b outputs a detection signal ER whose level becomes "B" during a period when the level of the signal TDT and the level of the signal RDT do not match.The timing at which this detection signal ER is generated is based on the internal clock It changes depending on the phase relationship between CLK and the dot clock DCKS.First, we will explain the case where the phase of the dot clock DCKS lags behind the internal clock CLK, as in the case (a) in Fig. 4. In this case, the detection signal ER rises in synchronization with the change in the signal TDT and falls in synchronization with the change in the signal RDT.Therefore, as the dot clock DCKS lags behind the internal clock CLK (in the direction of arrow R1), The fall of the detection signal ER is delayed (in the direction of arrow R2).Next, we will explain the case where the phase of the dot clock DCKS is ahead of the internal clock CLK, as in the case (b).In this case, the detection signal ER rises in synchronization with a change in the signal RDT and falls in synchronization with a change in the signal 'rDT.Therefore, the dot clock DCKS or the internal clock C
When it advances further than LK (in the direction of arrow F1), the detection signal ER rises earlier (in the direction of arrow F2) by the amount of advance. In this way, the period during which the detection signal ER is "1°" changes depending on the phase difference between the dot clock DCKS and the internal clock CLK. The result status display circuit l6 is an OR gate 16a.
, Schmitt trigger circuit 16b, flip-flop 16
Consists of c. Here, the Schmitt trigger circuit 16b is
This is provided to stabilize the operation of the result display circuit l6. The operation of the result status display circuit 16 in response to the detection signal ER will be described below. After the control data DTB is input to the aforementioned delay circuit I1, the test result read signal RTR is input to the clock skew adjustment circuit. This signal RTR clears the flip-flop 16c and resets the error signal ERST at that time. Therefore, at the time when the phase of the internal clock CLK is set and the phase comparison is started, the error signal E
RST is "0". In this state, when the detection signal ER changes, the change in this signal is caused by the OR gate! 6a1 sequentially propagate through the unit trigger circuit 16b,
The data input of flip-flop 16c changes. As in the case (c) in FIG. 4, when the fall of the detection signal ER is delayed due to the phase delay of the dot clock DCKS, the output level of the Schmitt trigger circuit l6b is "1" at the fall of the internal clock CLK.
Therefore, this level "1" is taken into the flip-flop 16c by the internal clock CLK, and the error signal ERST rises. And this error signal ER
ST is OR gate 16a and Schmitt trigger circuit 1
6b to the flip-flop 16c, the error signal ERST continues at level "1". After the error signal ERST is read, the test result read signal RTR is manually input to the flip-flop 16c.
is cleared. Here, if the falling point of the detection signal ER and the falling point of the internal clock CLK are very close to each other, a narrow pulse may be generated at the output of the 0 1j gate 16a. However, since the sensitivity of the Schmitt trigger circuit +6b is low, this pulse is not input to the flip-flop 16c, and the flip-flop 16c does not fall into unstable operation. Note that even if the phase of the dot clock DCKS leads the internal clock CLK, if the phase lead exceeds the limit, the detection signal ER (level "l"
”) is read into the flip-flop l6C, and the error signal ERST rises. By the way, as shown in FIG. 4, the signal delay time of the display control circuit 4a is large, and the dot signal is When VDT. changes, the error signal ERST is generated by an operation different from that described above.In other words, as shown in (d), the dot clock D
The phase of CKS advances and the dot signal VDT. When the dot signal VDT. At the end, data one cycle earlier than when the phase of the double clock DCKS is normal is read into the flip-flop 15a. As shown in FIG. 4, if the signal delay time when the dot VDTO falls is larger than the signal delay time when the dot VDTO rises, as shown in (d), the dot signal VDTO
T. As a result, "l" is read into the flip-flop 15a each time, and the signal RD'r continues to be "I". In this case, the signal T D 'r h< E
It is inverted by the OR gate 15b and output as the detection signal El"t, and as a result, the error signal ERS
T is generated. Contrary to the above, if the signal delay time at the falling edge of the dot signal VDTO is greater than that at the rising edge, the signal RDT becomes "0" and the error signal E
IIST is generated. In this way, in this clock skew adjustment circuit, when the phase difference between the dot clock DCKS and the internal clock CLK and the phase difference between the dot clock DCKS and the dot signal VDTO exceed a certain limit, the error signal E R S is generated.
'r is output. Then, as shown in (e), when the dot clock DCKS rises during the period SAFE surrounded by the limit in the phase advance direction and the limit in the phase delay direction, the error signal ERST is not output. As described above, in this clock skew adjustment circuit, a phase comparison is performed between the dot clock DCKS, the internal clock CLK, and the dot signal VDTO. and,
In this clock skew adjustment circuit, phase comparison is performed by changing the amount of delay in delay circuit II, and internal clock C
The phase of LK is adjusted, and when this phase adjustment is completed, the screen overlay system ends the clock skew adjustment mode and starts the normal display mode. In this mode, the test signal TST becomes "0". Then, dot data V Do ”V generated from the dot data generation circuit I7
Dn, the θth bit data VD. is selector I2
and the dot signal VDT. Further, other data VDI to VDn are outputted as a dot signal VDT via a buffer l4. And these dot signals V D T o = V D
Tn is sent to the invasion degree switching circuit 6 (FIG. 2), and the screens are displayed in an overlapping manner.

[Embodiment 2] FIGS. 5 and 6 explain a second embodiment of the present invention, and FIG. 5 shows the configuration of the phase detection circuit 15a and the resultant deafness display circuit 15b in the same embodiment. FIG. 6 is a time chart showing the operation of the circuit. This phase detection circuit 15a detects the phase difference between the dot clock DCKM of the display control circuit 4a and the dot clock DCKS of the display control circuit 5. When the clock skew adjustment mode is started, the test signal 't's'r becomes "!" and is input to the dot clocks DCKS and DCKM to the flip-flop 153 via AND gates +51 and 152. Here, as shown in (a), dot clock DCKS
If the phase of the dot clock DCKS is ahead of the phase of the dot clock DCKM, the signal level of the dot clock DCKS always becomes "1" at the rising edge of the dot clock DCKM. Therefore, in this case, the level of the phase detection signal FPD of flip-flop +53 becomes "1". In the result status display circuit 16a, the signal FPD is a Schmitt trigger circuit! 61 through flip-flop 162
is man-powered. And this signal is internal clock CLK
(The dot clock DCKM is this internal clock C L
It is output as a phase state signal PHST (level "1") at the rising edge of the phase state signal PHST (outputted in synchronization with K). On the other hand, as shown in (b), when the phase of the dot clock DCKS lags behind the phase of the dot clock DCKM, the signal level of the dot clock DCKS always becomes "0" at the rising edge of the dot clock DCKM. Therefore, in this case, the level of the phase detection signal FPD of flip-flop +53 becomes "0". Then, from the result status display circuit 16a, a phase status signal P of level "0" is output.
HST is output. In this clock skew adjustment circuit, the phase state signal P
By determining whether I-I ST is "l°" or "0", it is determined whether it is ahead or behind the dot clock DCKS or dot clock DCKM. The above judgment is made while variously switching the output timing of DCKM,
A boundary state in which the phase state signal P HST changes from "0" to "0" is detected. In this state, the dot clocks DCKM and DCKS
are almost in phase. In a system in which the dot clock DCKS is manually input to the priority switching circuit 6, as in the screen overlapping system shown in FIG.
Since it is desirable that the phase of CKS is slightly ahead of the phase of the dot clock DCK'M, the phase of the dot clock DCKM is adjusted to a phase slightly delayed from the above-mentioned boundary state. In this way, this clock skew adjustment circuit adjusts the phases of the double clocks DCKM and DCKS. In the embodiments described above, an example was explained in which the clock skew adjustment circuit of the present invention is applied to a screen overlapping system. It can also be applied when it is desired to adjust the phase of a signal. In addition, in the embodiments, the case where the clock skew adjustment circuit is provided in the display control circuit has been described, but it is also possible to realize part or all of the clock skew adjustment circuit in a separate LSI from the display control circuit. good. "Effects of the Invention" As explained above, according to the present invention, the phase detection means detects the phase difference between output signals of a plurality of control circuits, and the phase of the clock of each control circuit is adjusted according to the phase difference. Since a clock skew adjustment means for adjusting the clock skew is provided,
The phase of the output signal of each control circuit can be adjusted programmatically during initialization to properly synchronize the system. Therefore, it is no longer necessary to adjust the clock skew of each control circuit after manufacturing as in the conventional case, so that a synchronization system with stable operation can be efficiently manufactured.

[Brief explanation of the drawing]

FIG. 1 shows a clock skew adjustment circuit according to the first embodiment of the present invention! 2 is a block diagram showing the configuration of a screen overlapping system using the same embodiment, and FIG. 3 is a circuit diagram showing a specific example of the clock skew adjustment circuit 10 in the same embodiment. 4 is a time chart showing the operation of the circuit of FIG. 3, FIG. 5 is a circuit diagram of the phase detection circuit 15a and result status display circuit 16a in the clock skew adjustment circuit according to the second embodiment of the present invention, and FIG. 5 is a time chart showing the operation of circuit Q in FIG. 5, FIG. 7 is a block diagram showing the configuration of a general screen overlapping system, FIG. FIG. 9 is a time chart showing the phases of the output signals of display control circuits 4 and 5 in FIG. 10... Clock skew adjustment circuit, 15, l
5a... Phase detection circuit, 11... Delay circuit.

Claims (4)

[Claims] (1) In a synchronization system that includes a plurality of control circuits that are driven by a clock and output data signals synchronized with the clock, and performs synchronization based on each output signal of these control circuits, the plurality of control circuits A synchronization system comprising: a phase detection means for detecting a phase difference between output signals of each of the control circuits; and a clock skew adjustment means for adjusting a phase of a clock of each of the control circuits according to the phase difference. Clock skew adjustment circuit. (2) It has a plurality of display control circuits that are driven by a clock and outputs dot signals constituting the display screen and dot clocks synchronized with the dot signals, and the dot signals and dot clocks output from these display control circuits are A screen superimposition system that performs superimposed display of a plurality of screens on a display device based on the invention, comprising: phase detection means for detecting a phase difference between output signals of the plurality of display control circuits; and a phase detection means for detecting a phase difference between output signals of the plurality of display control circuits; 2. The clock skew adjustment circuit according to claim 1, further comprising clock skew adjustment means for adjusting the clock skew according to the phase difference. (3) The phase detection means detects a phase difference between a dot clock in a specific display control circuit among the plurality of display control circuits and a dot signal in another display control circuit. Clock skew adjustment circuit as described. (4) The clock skew adjustment circuit according to claim 2, wherein the phase detection means detects a phase difference between each dot clock output from the plurality of display control circuits.